Blog Review: October 25

LPDDR5X enhancements; MACsec components; validating AVs; verifying end-to-end properties.


Synopsys’ Graham Allan looks at enhancements in the LPDDR5X standard, such as a speed increase from 6.4Gbps to 8.5Gbps using the same 1.1V core voltage as LPDDR5 alongside better signal integrity, reliability, and battery efficiency.

Cadence’s Krunal Patel examines the essential components and operation of MACsec, a security protocol to ensure the confidentiality and integrity of data transmitted over Ethernet networks.

Siemens’ Alexandru Forrai finds that the increased complexity of automated vehicles necessitates a radical change of test methods and new concepts for verification and validation in both the physical and the virtual world and introduces a multi-pillar approach for safety validation.

Codasip’s Laurent Arditi explores formal verification with a look at how to verify powerful assertions and prepare the formal testbench to verify end-to-end properties, along with some best practices.

Arm’s Parag Beeraka checks out new applications being enabled by computer vision technologies and some of the challenges, such as bandwidth and data management, in deploying them.

Ansys’ Bernard Dion points to the combined role of AI/ML and simulation in building safer autonomous advanced air mobility systems and how simulation can improve both perception training and decision-making training to strengthen flight performance, the safety of flight maneuvers, and collision avoidance.

Keysight’s Chaimaa Aarab notes the role of lidar in automotive sensor systems and the need to test lidar systems to ensure they can quickly and reliably detect objects.

SEMI’s Jaegwan Shim shares highlights from the recent SEMI Korea Members Day, including predictions for when the global semiconductor market will rebound and growth in power semiconductors.

IBM’s Mike Murphy details the company’s latest digital AI chip architecture for neural inference, which places all of the memory for the device is on the chip itself to avoid the von Neumann bottleneck.

Plus, check out the blogs featured in the latest Manufacturing, Packaging & Materials newsletter:

Lam Research’s QingPeng Wang lays out how virtual fabrication can help identify process margins and provide guidance for inline process spec control.

D2S’ Jan Willis predicts that automatic curvy routing and parasitic extraction will be essential, while DRC may become easier.

ESD Alliance’s Bob Smith asks why EDA doesn’t go through the same boom and bust cycles as the larger semiconductor industry.

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