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Blog Review: Sept. 18

ML benchmarking; NVDIMM; physics of failure.

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Cadence’s Paul McLellan checks out MLPerf and the challenges involved in developing a benchmark to assess machine learning training and inference performance.

Synopsys’ Om Prakash Thakur and Nusrat Ali take a look at the different types of NVDIMM and how it can bridge the performance gap between memory and storage solutions in servers.

Mentor’s Matthew Ballance points to why adoption of Portable Stimulus may mirror that of electric and hybrid vehicles by offering more than one path to increase efficiency.

ANSYS’ Craig Hillman explains how the physics of failure approach and reliability physics analysis are used to optimize the performance, reliability and durability of electronics.

SEMI’s Christian G. Dieseldorff takes a look at the upcoming jump in fab construction, with 15 new fab projects slated to begin this year and another 18 beginning in 2020, to see what they’ll produce, which wafer size they’ll use, and where the investment is coming from.

Lam Research’s Nerissa Draeger provides an overview of scaling in transistors, interconnects, and memory, what some of the biggest challenges for continued improvement are, and potential solutions.

A Rambus writer points to a newly published malware attack targeting Intel’s Software Guard Extension (SGX) that exploits a separation between the build and signing processes to potentially alter the behavior of a secure enclave.

Arm’s Hellen Norman presents a primer on the basics of training and inference in convolutional neural networks.

Intel’s David Hoffman argues that it’s time for the U.S. Congress to take up a comprehensive federal privacy law to protect consumers that goes beyond just transparency to address harmful usage of personal data and hold bad actors accountable.

Plus, check out the blogs highlighted in the latest Low Power-High Performance newsletter:

Editor In Chief Ed Sperling observes that what was once a progression of bottlenecks and technology issues has turned into a minefield.

Rambus’ Steven Woo shows why memory is no longer able to keep pace with raw compute capability, creating a bottleneck that grows larger each year.

Synopsys’ Graham Wilson reviews how DSPs evolved to support the demands of new mobile communication standards.

Adesto’s Paul Hill and Gordon MacNee demonstrate how to integrate power control circuitry into the memory device itself, allowing the master device to control the power mode via serial flash SPI.

Mentor’s Allan Crone makes the case for a new place and route flow that produces fast results out of the box and allows for full flow customization.

Arteris IP’s Kurt Shuler contends that AI demands are pushing innovation in design architectures and techniques.

Cadence’s Rohit Kapur finds that while scan compression is a critical technology used in nearly every design, it doesn’t come without costs.

OptimalPlus’ Peter Hodgins notes that the need for high quality automotive cameras is rising, and new technologies can help the manufacturing process become more efficient.



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