Intent Meets Implementation
By Siemens EDA - 15 May, 2025 - Comments: 0

Power efficiency has become a must-have in today’s ASIC and SoC designs. It’s no longer just about squeezing out more performance. It’s about doing so without draining the battery, wasting energy or overheating the system. Whether the chip is headed for a smartphone, a server rack in an AI datacenter or the control system of an autonomous vehicle, managing power wisely is as critical as m... » read more

Optimizing Analog With Layout In The Loop
By Benjamin Prautsch - 15 May, 2025 - Comments: 0

Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle
By Chandu Challapalli - 15 May, 2025 - Comments: 0

As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

HBM4 Elevates AI Training Performance To New Heights
By Nidish Kamath - 15 May, 2025 - Comments: 0

Generative and Agentic AI are pushing an extremely rapid evolution of computing technology. With leading-edge LLMs now in excess of a trillion parameters, training takes an enormous amount of computing capacity, and state-of-the-art training clusters can employ more than 100,000 GPUs. High Bandwidth Memory (HBM) provides the vast memory bandwidth and capacity needed for these demanding AI train... » read more

Trapped By Legacy
By Steve Roddy - 15 May, 2025 - Comments: 0

At Quadric, we do a lot of first-time introductory visits with prospective new customers. As a rapidly expanding processor IP licensing company that is starting to get noticed (even winning IP Product of the Year!) such meetings are part of the territory. Which means we hear a lot of similar-sounding questions from appropriately skeptical listeners who hear our story for the very first time. Th... » read more

Deploying PyTorch Models On Edge Devices
By Cornelius Maroa - 15 May, 2025 - Comments: 0

AI is being rapidly adopted in edge computing. As a result, it is increasingly important to deploy machine learning models on Arm edge devices. Arm-based processors are common in embedded systems because of their low power consumption and efficiency. This tutorial shows you how to deploy PyTorch models on Arm edge devices, such as the Raspberry Pi or NVIDIA Jetson Nano. Prerequisites Before y... » read more

Die-to-die Interconnect Standards In Flux
By Bryon Moyer - 15 May, 2025 - Comments: 0

UCIe, a standard for die-to-die interconnect in advanced packages, has drawn concern about being too heavyweight with its 2.0 release. But the fact that many of the new features are optional seems to have been lost in much of the public discussion. In fact, new capabilities that support a possible future chiplet marketplace are not required for designs that don’t target that marketplace. ... » read more

High-Speed Test IO: Addressing High-Performance Data Transmission And Testing Needs For HPC & AI
By Lakshmi Jain - 15 May, 2025 - Comments: 0

By Lakshmi Jain and Wei-Yu Ma The AI and HPC industries are rapidly shifting toward chiplet-based designs to achieve unprecedented levels of performance, as traditional monolithic system-on-chip (SoC) architectures face scaling limitations. This transition is fueled by the rise of heterogeneous integration, which is driving innovation across the semiconductor sector. However, this advancemen... » read more

Development Flows For Chiplets
By Brian Bailey - 15 May, 2025 - Comments: 0

Chiplets offer a huge leap in semiconductor functionality and productivity, just like soft IP did 40 years ago, but a lot has to come together before that becomes reality. It takes an ecosystem, which is currently very rudimentary. Today, many companies have hit the reticle limit and are forced to move to multi-die solutions, but that does not create a plug-and-play chiplet market. These ear... » read more

UALink: Powering The Future Of AI Compute
By Sangeeta Soni - 15 May, 2025 - Comments: 0

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification, marking an important milestone with support from key hyperscalar market players. It enables a low-latency, high-bandwidth fabric that supports hundreds of accelerators in a pod and facilitates simple load-and-store semantics. Motivation behind UALink The rapid evolution of Artificial Intelligence (AI) an... » read more

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