Viability of aZnMIm As A Resist For EUV Lithography (Johns Hopkins, Northwestern, Intel et al.)
By Technical Paper Link - 27 Jun, 2025 - Comments: 0

A new technical paper (preprint) titled "Extreme Ultraviolet and Beyond Extreme Ultraviolet Lithography using Amorphous Zeolitic Imidazolate Resists Deposited by Atomic/Molecular Layer Deposition" was published by researchers at Johns Hopkins University, Northwestern University, Intel Corporation, Bruker Nano, EUV Tech and Lawrence Berkeley National Lab. The paper states "This study demonstr... » read more

Chip Industry Week in Review
By The SE Staff - 27 Jun, 2025 - Comments: 0

AI featured big at this week's Design Automation Conference (DAC) in San Francisco. Dozens of companies featured AI-related tools (see product section below), as well as significant improvements to existing tools and some entirely new approaches for designing chips. Among the highlights: Siemens unveiled an AI-enhanced toolset for the EDA design flow that enables customers to integrate the... » read more

GNN-Based Framework for Hardware Trojan Detection, Including RISC-V Cores
By Technical Paper Link - 26 Jun, 2025 - Comments: 0

A new technical paper titled "TROJAN-GUARD: Hardware Trojans Detection Using GNN in RTL Designs" was published by researchers at University of Connecticut and University of Minnesota. Abstract "hip manufacturing is a complex process, and to achieve a faster time to market, an increasing number of untrusted third-party tools and designs from around the world are being utilized. The use of th... » read more

Iteration And Hallucination
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Iteration loops have been a vital aspect of EDA flows for decades. Ever since gate delays and wire delays became comparable, it became necessary to find out if the result of a given logic synthesis run would yield acceptable timing. Over the years this problem became worse because one decision can affect many others. The ramifications of a decision may not have been obvious to an individual too... » read more

Mixed Messages Complicate Mixed-Signal
By Brian Bailey - 26 Jun, 2025 - Comments: 0

Several years ago, analog and mixed signal (AMS) content hit a wall. Its contribution to first-time chip failure doubled, and there is no evidence that anything has improved dramatically since then. Some see that the problem is likely to get worse due to issues associated with advanced nodes, while others see hope for improvement coming from AI or chiplets. Fig. 1: Cause of ASIC respins. S... » read more

Redefining SoC Design: The Shift To Secure Chiplet-Based Architectures
By Moshiko Emmer - 26 Jun, 2025 - Comments: 0

The semiconductor industry is undergoing a paradigm shift from monolithic system-on-chip (SoC) architectures to modular, chiplet-based designs. This transformation is driven by escalating design complexity, soaring fabrication costs, and the relentless pursuit of efficiency. However, as chiplet adoption accelerates, security becomes a critical concern, requiring robust measures to protect data,... » read more

Distributing Intelligence Inside Multi-Die Assemblies
By Ed Sperling - 26 Jun, 2025 - Comments: 0

The shift from SoCs to multi-die assemblies requires more and smarter controllers to be distributed throughout a package in order to ensure optimal performance, signal integrity, and no downtime. In planar SoCs, many of these kinds of functions are often managed by a single CPU or MCU. But as logic increasingly is decomposed into chiplets, connected to each other and memories by TSVs, hybrid... » read more

Programmable Hardware Delivers 10,000X Improvement In Verification Speed Over Software For Forward Error Correction
By Tony Chan Carusone - 26 Jun, 2025 - Comments: 0

In the race to increase the speeds of wireline networking and communications, forward error correction (FEC) has become a vital part of the toolkit. To function effectively, especially with the increasing use of four-level pulse amplitude modulation (PAM4), high-speed protocols need FEC to avoid a rise in the number of reception errors. Each incremental increase in the transmitted symbol rate r... » read more

Security Vulnerabilities Difficult To Detect In Verification Flow
By Ann Mutschler - 26 Jun, 2025 - Comments: 0

As designs grow in complexity and size, the landscape for potential hackers to infiltrate a chip at any point in either the design or verification flow increases commensurately. Long considered to be a “safe” aspect of the design process, verification now must be a focus of chip developers from a security perspective. This also means the concept of trust has never been higher, and the tr... » read more

Disruptive Changes Ahead For Photomasks?
By Gregory Haley - 25 Jun, 2025 - Comments: 1

Experts at the Table: Semiconductor Engineering sat down with four experts to explore the current state and future direction of mask-making, with insights from Harry Levinson, principal lithographer at HJL Lithography; Aki Fujimura, CEO of D2S; Ezequiel Russell, senior director of mask technology at Micron; and Christopher Progler, executive vice president and CTO at Photronics. What follows ... » read more

← Older posts

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy