In-Design Rail Analysis Is A Beautiful Thing


As a long time designer, ASIC flows amaze me and making them better is my goal. Although a very complex and intricate process, each part of the ASIC flow abstracts the complexity underneath it to ultimately create silicon that could end up in your smartwatch, your electric vehicle, or the latest cell phone – how amazing! Consumers concerns include product reliability and robustness, which bri... » read more

Deep Learning Market Forces


Last week, eSilicon participated in a deep learning event at the Computer History Museum – “ASICs Unlock Deep Learning Innovation.” Along with Samsung, Amkor Technology and Northwest Logic, we explored how our respective companies form an ecosystem to develop deep learning chips for the next generation of applications. We also had a keynote presentation on deep learning from Ty Garibay, C... » read more

Simplifying SystemVerilog Functional Coverage


Let’s say you have a block you need to verify. How do you know that the stimulus you are about to use is exhaustive enough and that you have covered the necessary scenarios/situations to prove it is working correctly? This is where functional coverage comes in. SystemVerilog’s functional coverage constructs allow you to quantify the completeness of your stimulus by recording the values that... » read more

Can Big Data Help Coverage Closure?


Semiconductor designs are a combination of very large numbers and very small numbers. There is a large numbers of transistors at very small sizes, and databases are often large. The chip industry has been looking at [getkc id="305" kc_name="machine learning"] to effectively manage some of this data, but so far datasets have not been properly tagged across the industry and there is a reluctan... » read more

Embedded World 2018: Security, Safety, And Digital Twins


This year's embedded world in Nuremberg was again very well attended despite a cold wave in Europe. The key trends I had expected to see were safety and security, and the exhibits did not disappoint. One additional key theme that stood out to me was that of “digital twinning.” And, of course, the battle of processor ecosystems does continue. RISC-V has joined the games and feels a bit like ... » read more

Tech Talk: Automotive Design


NetSpeed Systems CEO Sundari Mitra talks about how to speed up the design of automotive chips. https://youtu.be/cus4fStDa5c » read more

Applying Machine Learning To Chips


The race is on to figure out how to apply analytics, data mining and machine learning across a wide swath of market segments and applications, and nowhere is this more evident than in semiconductor design and manufacturing. The key with ML/DL/AI is understanding how devices react to real events and stimuli, and how future devices can be optimized. That requires sifting through an expandi... » read more

Asterix In The Land Of Sudoku: The Fast, The Elegant, And The Popular Formal Solvers


It has become a time-honored tradition for OneSpin to pose a holiday puzzle challenge to engineers everywhere. Last year, we asked you to solve the famous Einstein riddle using assertions and a formal tool: It was a great success. For the 2017–18 holiday season, we asked you to solve the hardest Sudoku in the world and prove that the solution is unique. We are delighted that even more enthusi... » read more

Tech Talk: Faster Simulation


Cadence’s Adam Sherer talks about how to speed up simulation in complex multi-core designs. https://youtu.be/lDgMwU5KN7U » read more

Merging Verification With Validation


Verification and validation are two important steps in the creations of electronic systems and over time their roles, but how they play together is changing. In fact, today we are seeing a major opportunity for rethinking this aspect of the flow, which could mean the end of them as separate tasks for many of the chips being created. As with many things in this industry, however, squeezing it... » read more

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