10 CFD Simulations To Try Out This Winter
By Veena Parthan - 09 Jan, 2025 - Comments: 0

As winter settles in and the snowflakes begin to fall, it's time to dust off those curious minds and prepare for some seriously fun—and slightly nerdy—computational fluid dynamics (CFD) simulations! Whether you’re a CFD expert or a beginner looking for scientific flair, here are ten simulations that will warm your winter spirit and challenge your brain cells. Snowflake dynamics: N... » read more

Fully Coupled CFD Simulations for Micro Gas Turbine Engines
By Cadence - 09 Jan, 2025 - Comments: 0

This conference paper offers a detailed exploration of the fully coupled CFD simulation of a KJ66 micro gas turbine (MGT) engine—an innovative approach that enhances the accuracy and fidelity of 3D numerical analysis. Key Takeaways: Integrated Approach: Unlike traditional component-by-component analysis, fully coupled simulations account for the interactions between the compressor, co... » read more

Power And Sensing Selection Guide 2024-2025
By Infineon - 09 Jan, 2025 - Comments: 0

This latest edition of the power & sensing selection guide compares our products’ key benefits and the latest power and sensing technology advancements to find what you need for your designs. Technologies covered include: MOSFETs, MCUs, power management ICs, wide-bandgap semiconductors, sensors, power switches, USB-C and more. Read more here. » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools
By Technical Paper Link - 08 Jan, 2025 - Comments: 0

A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

Startup Funding: Q4 2024
By Jesse Allen - 08 Jan, 2025 - Comments: 0

The fourth quarter of 2024 saw five mega-rounds of over $100 million. One of the hottest areas continues to be AI hardware, with one company developing RISC-V AI processor IP bringing in nearly $700 million in the largest round for a chip design startup this year. It was far from the only AI startup, however, as several companies gathered support for neuromorphic designs focused on ultra-low po... » read more

Blog Review: Jan. 8
By Jesse Allen - 08 Jan, 2025 - Comments: 0

Cadence's Igor Krause unravels the different Orthogonal Header Content (OHC) types in PCIe 6.0, which work as an extra header for the Transaction Layer Packet (TLP) that incorporates information fields that are needed depending on the TLP type. Siemens EDA's Yunhong Min considers how AI and machine learning are reshaping functional verification workflows from translating specifications to de... » read more

Research Bits: Jan. 7
By Jesse Allen - 07 Jan, 2025 - Comments: 0

Deep UV microLED for maskless lithography Researchers from the Hong Kong University of Science and Technology, Southern University of Science and Technology, and the Suzhou Institute of Nanotechnology developed an aluminum gallium nitride deep-ultraviolet microLED display array for maskless lithography.  They also built a maskless lithography prototype platform. "The team achieved key brea... » read more

Chip Industry Technical Paper Roundup: Jan. 7
By Linda Christensen - 07 Jan, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=395 /] Find all technical papers here. » read more

Designing Heterogeneous AI Acceleration SoCs
By Technical Paper Link - 06 Jan, 2025 - Comments: 0

A new technical paper titled "Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience" was published by researchers at University of Bologna. Abstract "Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor co... » read more

What’s Next For Through-Silicon Vias
By Laura Peters - 06 Jan, 2025 - Comments: 0

From large TSVs for MEMS to nanoTSVs for backside power delivery, cost-effective process flows for these interconnects are essential for making 2.5D and 3D packages more feasible. Through-silicon vias (TSVs) enable shorter interconnect lengths, which reduces chip power consumption and latency to carry signals faster from one device to another or within a device. Advanced packaging technology... » read more

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