Chiplet-to-Chiplet Gateway Architecture, A C2C Interface Bridging Two Chiplet Protocols (Peter Grünberg, Jülich Supercomputing Centre)


A new technical paper titled "Modeling Chiplet-to-Chiplet (C2C) Communication for Chiplet-based Co-Design" was published by researchers at Peter Grünberg Institute and Jülich Supercomputing Centre. Abstract "Chiplet-based processor design, which combines small dies called chiplets to form a larger chip, enables scalable designs at economical costs. This trend has received high attention s... » read more

Offline RL Framework That Dynamically Controls The GPU Clock And Server Fan Speed To Optimize Power Consumption And Computation Time (KAIST)


A new technical paper titled "Power Consumption Optimization of GPU Server With Offline Reinforcement Learning" was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and KT Research and Development Center. "Optimizing GPU server power consumption is complex due to the interdependence of various components. Conventional methods often involve trade-offs: in... » read more

Electrical Properties of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts (NYCU)


A new technical paper titled "Electrical Characteristics of ML and BL MoS2 GAA NS FETs With Source/Drain Metal Contacts" was published by researchers at National Yang Ming Chiao Tung University. Abstract "This paper reports source/drain (S/D) contact issues in monolayer and bilayer (BL) MoS2 devices through density-functional-theory (DFT) calculation and device simulation. We begin by ana... » read more

A Lightweight Scan Instrumentation For Enhancing The Post-Silicon Test Efficiency in ICs (U. of Florida)


A technical paper titled "Enhancing Test Efficiency through Automated ATPG-Aware Lightweight Scan Instrumentation" was published by researchers at University of Florida. Abstract "Scan-based Design-for-Testability (DFT) measures are prevalent in modern digital integrated circuits to achieve high test quality at low hardware cost. With the advent of 3D heterogeneous integration and chiplet-b... » read more

Role of Josephson Junctions In Propelling Quantum Technologies Forward (LBNL, UC Berkeley, et al.)


A new technical paper titled "Josephson Junctions in the Age of Quantum Discovery" was published by researchers at Lawrence Berkeley National Laboratory, UC Berkeley, Gwangju Institute of Science and Technology, Korea University, Max Planck and Anyon Computing. Abstract "The unique combination of energy conservation and nonlinear behavior exhibited by Josephson junctions has driven transfor... » read more

Chip Industry Week in Review


The U.S. Commerce Department is tightening controls on EDA software sold to China by imposing additional license requirements. EDA companies are assessing the impact. Details on how broad the restrictions will be are still pending. The U.S. Federal Trade Commission (FTC) will require Synopsys and Ansys to divest key software assets — including optical, photonic, and RTL power analysis tool... » read more

The DAC Valuation


The Design Automation Conference is approaching fast, and the evidence of a funding gap is in plain sight. An entire day of the technical conference has been dropped. This is disheartening to say the least, and in the long term it may be a very costly mistake. The problems started when the Internet bubble burst in 2000. Until then, DAC was growing to the point whereby few convention halls we... » read more

Addressing Stress In Heterogeneous 3D-IC Designs


The benefits of 3D IC architectures are well-documented – smaller footprints, lower power, and increased performance. However, the move to heterogeneous 3D designs also introduces a host of new challenges that must be carefully navigated. As chip designers integrate multiple dies and technologies into a single 3D package, the interactions between the chip and package become increasingly co... » read more

Closing The RISC-V Verification Disconnect


With the explosive adoption of RISC-V processors, processor verification has become a hot topic. This is due both to the criticality of the processor IP in the SoC and to the fact that many experienced SoC verification engineers are doing their first processor verification project. While there are similarities between SoC verification and processor verification, there are also significant diffe... » read more

Optimizing Data Movement


Demand for new and better AI models is creating an insatiable demand for more processing power and much better data throughput, but it's also creating a slew of new challenges for which there are not always good solutions. The key here is figuring out where bottlenecks might crop up in complex chips and advanced packages. This involves a clear understanding of how much bandwidth is required ... » read more

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