Features And Benefits Of The SECS/GEM Standard – eBook


Discover how the SEMI E30 SECS/GEM standard empowers smarter, more efficient manufacturing by enabling factories to seamlessly collect equipment data, reduce integration costs, implement advanced process control, and improve overall operational performance. This eBook walks through key GEM capabilities—including collection events, alarms, recipe management, terminal services, and more—to s... » read more

Research Bits: May 11


Non-destructive terahertz inspection Researchers from Adelaide University, Virginia Diodes, the Hasso Plattner Institute, and the University of Potsdam used terahertz waves to observe electrical activity inside fully packaged semiconductor devices as they are operating. The technique relies on an ultra-sensitive detection system using a specialized homodyne quadrature receiver, which can pi... » read more

Chip Industry Technical Paper Roundup: May 11


New technical papers recently added to Semiconductor Engineering’s library: Technical Paper Research Organizations Source-position-dependent transmission cross coefficient formula including polarization and mask three-dimensional effects in High NA EUV🔗 Science Tokyo Performance and Energy Benefits of MRDIMMs 🔗 Barcelona Supercomputing Center, UPC, ... » read more

Chip Industry Week In Review


Manufacturing ASE and WUS are jointly building a ~$1.1B advanced packaging hub in Kaohsiung, Taiwan, for fan-out chip-on-substrate (FOCoS) and flip-chip ball grid array (FC BGA) technologies. The new site is expected to be completed by September 2029. SpaceX filed documents for a “Terafab” semiconductor manufacturing and computing facility at Gibbons Creek Reservoir in Texas, with a... » read more

The Emergence Of Electronics Digital Twins For Software-Defined Vehicles


Digital twins have long played a critical role in engineering and manufacturing. As virtual representations of physical products, systems, and processes, they help organizations innovate faster, improve quality, and reduce costs. Early digital twin technologies were primarily rooted in the physical world, modeling mechanical systems such as engines, buildings, and factory operations to simulate... » read more

Securing Chiplet-Based Platforms: Distributed Trust With Centralized Authority


In previous blogs, From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm, and Developing a Security Framework for Chiplet-based Systems, we discussed why chiplets change the game from a security perspective, and why security must be addressed at a platform-level in a chiplet-based system. In a monolithic device, trust is often implicitly bounded by the die itself: sensitive asse... » read more

Powering AI At Scale: Why 3D-ICs Demand A New Approach To Power Integrity


By Muhammad Hassan and Sudarshan Deo The semiconductor industry is undergoing a fundamental transition. Performance scaling is no longer driven primarily by transistor density, but by advanced packaging—2.5D, 3D-ICs, chiplets, and heterogeneous integration. Fig. 1: 3D-IC and 2.5D structure. These architectures are essential to meeting the extreme performance and bandwidth demands... » read more

How OCP S.O.L.I.D. Completes The Data Center Security Picture


In 2023, the Open Compute Project launched S.A.F.E. (Security Appraisal Framework and Enablement), a standardized process for auditing data center hardware and firmware. It delivered something the industry needed: approved third-party reviewers, continuous assessments, and public reports — not just one-time certifications. S.A.F.E. provided the audit framework; what it did not provide was gui... » read more

Building AI Without Guardrails


Key Takeaways: AI governance is broadly recognized as essential, but today it remains fragmented, largely aspirational, and lacking enforceable mechanisms for accountability, runtime assurance, and global interoperability. Because AI innovation is advancing too quickly for governments or standards bodies to keep pace, practical AI governance is most likely to emerge first from high‑ri... » read more

2.5D + 3D = “3.5D”!


The semiconductor industry is no longer defined solely by transistor scaling. As Moore's law decelerates, advanced packaging has become the primary lever for achieving system-level performance gains. Within this landscape, the equation 2.5D + 3D = 3.5D—defying the instincts of basic math and physics—captures a pivotal architectural evolution: one that balances performance, manufacturabilit... » read more

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