Complete End-To-End Closed-Loop Product Yield Ramp And Learning
By Guy Cortez - 12 May, 2026 - Comments: 0

By Guy Cortez and Maheshwaran Jothi Yield ramp has always been a concern in semiconductor manufacturing: systems companies need confidence that devices meet quality targets before shipment, and chipmakers need to reach yield entitlement quickly to control cost and supply. While this has never been easy, advanced nodes are raising the bar again. First, designs are larger and more heterogen... » read more

Test Distribution Evolves To Meet AI Challenges
By Fabio Pizza - 12 May, 2026 - Comments: 0

The proliferation of artificial intelligence (AI) is driving rapid acceleration of the semiconductor market, which analysts now predict will reach $1 trillion this year. Many semiconductor devices will be the GPUs that populate the data centers that run AI workloads. Driven by strong, sustained investments from hyperscaler operators, high-performance computing (HPC)/AI data centers are expected... » read more

Ensuring AI Reliability: Mitigating Silent Data Corruption Risks
By Noam Brousard - 12 May, 2026 - Comments: 0

Silent Data Corruption (SDC) is an industry challenge affecting data centers worldwide with increasing frequency. This phenomenon stems from untraceable hardware failures that make detection notoriously difficult. SDCs don’t leave any record in system logs or trigger exception mechanisms. The corrupted data they produce can propagate unnoticed, causing cascading failures that often demand ext... » read more

AI Accelerator Testing Depends On DFT Innovations
By Laura Peters - 12 May, 2026 - Comments: 0

Key Takeaways: I/O and lane repair capabilities are becoming critical to improving yield. System-level testing catches marginal defects and rare defects such as silent data corruption errors. Synopsys and TSMC developed a multi-die demo vehicle capable of full test, monitor, debug, and repair capability across the system’s lifecycle. The proliferation of accelerators in AI... » read more

Advanced Metrology for Backside Metallization Using Picosecond Laser Ultrasonics
By Onto Innovation - 12 May, 2026 - Comments: 0

Picosecond Ultrasonics (PULSE) Technology has emerged as a leading metrology solution for characterizing single-layer and multilayer metal films in advanced semiconductor manufacturing [1]. As a non-contact, non-destructive technique, PULSE Technology has become the tool-of-record across multiple device segments, including logic, radio frequency (RF), memory, microelectromechanical systems (MEM... » read more

The AI Server Challenge: Testing Power At Scale
By Aik-Moh Ng - 12 May, 2026 - Comments: 0

Artificial intelligence is most often framed as a story of compute advancements. Faster GPUs, denser accelerators, and advanced process nodes. But behind every AI workload, the most fundamental constraint is power. Fig. 1: AI server market. Source: Grand View Research As AI servers scale to meet data center demand, power delivery is becoming one of the most critical and complex engine... » read more

Home Win: Challenging The Traditional Semiconductor Manufacturing Model
By Chris Rand - 12 May, 2026 - Comments: 0

Across Europe, many of us have grown accustomed to a model where semiconductor products, subassemblies and components are sourced from the Far East almost by default. The rationale has always been clear: significantly lower labor and manufacturing costs made offshore supply the most commercially viable option. Yet, while this approach has long been convenient, it has never been without compromi... » read more

Smart Test Collides With The Data Chain
By Gregory Haley - 12 May, 2026 - Comments: 0

Key Takeaways: The promise of smart test is a data-chain problem before it is an algorithm problem. A device can pass every checkpoint and still carry a latent defect the test record never captured. As test grows more adaptive, the validity of the measurement environment matters as much as the measurement itself. For years, the test roadmap has pointed toward more adaptive f... » read more

HBM Shifts Testing Left To Preserve AI Chip Yield
By Anne Meixner - 12 May, 2026 - Comments: 1

Key Takeaways: A high-yield, known-good stack requires multiple test insertions. Known good stack testing poses challenges for power delivery and thermal management. The shift to HBM4 and HBM5 will increase the pressure for shift-left test flows. Taller high-bandwidth memory (HBM) stacks and tighter TSV pitch are impacting AI module yields. The solution is to push test furth... » read more

Debugging Modern SoCs With Embedded Analytics: Instrumentation, Trace, And Faster Root-Cause Isolation
By Mike Sharp - 12 May, 2026 - Comments: 0

As SoCs chase ever higher performance and power efficiency, their designs have become harder to rootcause and harder to debug. Today’s devices combine billions of transistors with heterogeneous compute blocks and a growing mix of third‑party IPs, so failures can come from anywhere: a corner-case interaction between cores, an integration mistake, a timing assumption that no longer holds, or ... » read more

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