Chip Industry Technical Paper Roundup: May 11

High-NA EUV litho; MRDIMM performance; GPU power estimation for AI workloads; RISC-V verification; inverse-designed grating couplers; SDV drive architectures; multi-chiplet memory-centric attention serving; GAA transistor leakage.

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New technical papers recently added to Semiconductor Engineering’s library:

Technical Paper Research Organizations
Source-position-dependent transmission cross coefficient formula including polarization and mask three-dimensional effects in High NA EUV🔗 Science Tokyo
Performance and Energy Benefits of MRDIMMs 🔗 Barcelona Supercomputing Center, UPC, Micron, Intel
EnergAIzer: Fast and Accurate GPU Power Estimation Framework for AI Workloads 🔗 MIT, IBM Research
Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL 🔗 Barcelona Supercomputing Center
Multimode grating couplers via foundry-compliant inverse design 🔗 Yale University
Modular Drive Architecture for Software-defined Vehicles Enabled by Power-packet-based Sensorless Control 🔗 Kyoto University
AMMA: A Multi-Chiplet Memory-Centric Architecture for Low-Latency 1M Context Attention Serving 🔗 UC San Diego, Columbia University, Yonsei University, Nvidia, Samsung
Gate-Drain Leakage Enhanced by Drain-Induced Dielectric Barrier Lowering in GAAFETs 🔗 Sandia National Lab, Luxembourg Institute of Science and Technology

Find more semiconductor research papers here and the latest chip industry news here.



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