The Trouble With Triples—Part 1
By David Abercrombie - 14 Nov, 2013 - Comments: 0

If you’re a true geek like me, you may remember the Star Trek episode “The Trouble with Tribbles,” about the cute furry little aliens that purr when you pet them. They seemed so nice and friendly on the surface, but in the end, they became an exponentially growing mass of ravenous monsters that almost broke down the ship and consumed the storehouse of grain that was meant to provide human... » read more

More 3D Printing Applications
By Michael Watts - 14 Nov, 2013 - Comments: 0

There is enough news about 3D printing that the Guardian newspaper’s Web site even has a special section on it. The list of demonstrated applications runs the gamut from guns to panties via custom bobble head dolls and organs. It's interesting to look at all these ideas and try and work out which really has potential. There are 3 categories for potential: Practical. Possible with inv... » read more

Crunch Time
By Brian Fuller - 14 Nov, 2013 - Comments: 0

The electronics industry finds itself today at a tipping point (well, okay, another tipping point). Consider:  The network as we’ve known it for a couple of generations is changing before our eyes, not the least of which to accommodate the expected explosion of Internet of Things in the coming years. ARM CEO Simon Segars put it this way at the recent ARM TechCon event in Santa Clara: ... » read more

Tunnel FETs Emerge In Scaling Race
By Mark LaPedus - 14 Nov, 2013 - Comments: 2

Traditional CMOS scaling will continue for the foreseeable future, possibly to the 5nm node and perhaps beyond, according to many chipmakers. In fact, chipmakers already are plotting out a path toward the 5nm node, but needless to say, the industry faces a multitude of challenges along the road. Presently, the leading transistor candidates for 5nm are the usual suspects—III-V finFETs; gate... » read more

Improve Logic Test With A Hybrid ATPG/BIST Solution
By Various Writers - 14 Nov, 2013 - Comments: 0

Two test strategies are used to test virtually all IC logic—automatic test pattern generation (ATPG) with test pattern compression, and logic built-in self-test (BIST). For many years, there was a passionate debate between some DFT practitioners about which is the best test method— ATPG or BIST. ATPG has been dominant for years, and is now used for full-chip test across the electronics indu... » read more

What’s After 10nm?
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, chipmakers have roughly doubled the transistor count at each node, while simultaneously cutting the cost by around 29%. IC scaling, in turn, enables faster and lower cost chips, which ultimately translates into cheaper electronic products with more functions. Consumers have grown accustomed to the benefits of Moore’s Law, but the question is for how much longer? Chips based ... » read more

Momentum Builds For Monolithic 3D ICs
By Mark LaPedus - 14 Nov, 2013 - Comments: 1

The 2.5D/3D chip market is heating up on several fronts. On one front, stacked-die using through-silicon vias (TSVs) is taking root. In a separate area, Samsung is sampling the world’s first 3D NAND device, with Micron and SK Hynix expected to follow suit. And now, there is another technology generating steam—monolithic 3D integrated circuits. In stacked-die, bare die are connected using... » read more

ARMing Intel
By Mark LaPedus - 14 Nov, 2013 - Comments: 0

For some time, the industry has kept a close eye on Intel’s fledging foundry business. The question is whether Intel will merely dabble in the foundry business or become a major player. The answer? It’s still too early to tell. Not long ago, Intel entered the foundry business and announced a smattering of small and niche-oriented customers, such as Achronix, Netronome and Tabula.  Micro... » read more

Blog Review: Nov. 13
By Ed Sperling - 13 Nov, 2013 - Comments: 0

Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops. Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the enti... » read more

Executive Viewpoint: Atoptech’s Jue-Hsien Chern
By Brian Bailey - 13 Nov, 2013 - Comments: 0

What is the difference between skyscrapers and chips? Dr Chern has worked on both and he says it’s all about how you apply margins. Jue-Hsien Chern started his technology career earning a M.S. and B.S. in Engineering from National Taiwan University and majored in structural engineering — bridges, dams, tunnels and high-rise buildings, all of which had to withstand earthquakes. That is a ... » read more

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