Blog Review: Nov. 13

Traveling salesmen; outside the package; train wrecks; bugs; flowers; Canadian memory expertise.


Synopsys’ Brent Gregory digs into optimal paths—in this case between the bakery, the library and another store. This is the classic traveling salesman equation, but with a large sales staff and lots of stops.

Mentor’s Michael Ford points to the gap between supply-chain and shop-floor management solutions. This is yet another example of thinking outside the package—and maybe the entire industry—with tools that began in the semiconductor world.

Cadence’s Brian Fuller looks at the explosion in mobile data and what needs to be done to avoid a train wreck. All aboard!

Jasper’s Joe Hupcey does a video interview with his colleague, Scott Meeth, about formally verifying AMBA ACE cache-coherent designs—on the new ARM community site. This is all about flushing out hard-to-find bugs.

Real Intent’s Graham Bell is giving away orange roses in celebration of Halloween and Diwali. Welcome to the global village.

Synopsys’ Graham Allan explains why there is so much memory expertise just over the border in Canada. There’s some interesting history here.

And in case you missed last week’s Low Power-High Performance Newsletter, here are some noteworthy blogs:

Cadence’s Brian Fuller notes that a low-power crisis means both danger and opportunity in Japanese.

Synopsys’ Navraj Nandra digs deep into finFET impacts for reducing physical IP power consumption.

Apache Design’s Annapoorna Krishnaswamy looks at the current generation of FPGAs and why they pose new power and reliability challenges.

Nvidia’s Barry Pangrle examines the ARM Cortex-A53 and the impact of new standards and materials on performance and power.

Atrenta’s Ramesh Dewangan looks at the interaction between timing constraints and clock domain crossing.

Leave a Reply

(Note: This name will be displayed publicly)