Effects Of Reduced Refresh Latency On RowHammer Vulnerability Of DDR4 DRAM Chips
By Technical Paper Link - 04 Mar, 2025 - Comments: 0

A new technical paper titled "Understanding RowHammer Under Reduced Refresh Latency: Experimental Analysis of Real DRAM Chips and Implications on Future Solutions" was published by researchers at ETH Zurich, TOBB University of Economics and Technology, and University of Sharjah. Abstract "RowHammer is a major read disturbance mechanism in DRAM where repeatedly accessing (hammering) a row of... » read more

Chip Industry Technical Paper Roundup: Mar. 4
By Linda Christensen - 04 Mar, 2025 - Comments: 0

New technical papers recently added to Semiconductor Engineering’s library: [table id=410 /] Find more semiconductor research papers here. » read more

Research Bits: Mar. 4
By Jesse Allen - 04 Mar, 2025 - Comments: 0

Fiber computer Researchers from Massachusetts Institute of Technology (MIT), Rhode Island School of Design, and Brown University developed a programmable elastic fiber computer that could be woven into clothing to monitor health conditions and physical activity. Clothing created using the fiber computer was reported as comfortable and machine washable. The single elastic fiber computer cont... » read more

Wafer-Level Test Infrastructure for Higher Parallel Wafer Level Testing of SoC
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Design and Implementation of Test Infrastructure for Higher Parallel Wafer Level Testing of System-on-Chip" was published by researchers at Inha University and Teradyne. Abstract "Semiconductor companies have been striving to reduce their manufacturing costs. High parallelism is a key factor in reducing costs during wafer-level testing. Wafer testing is conduct... » read more

Synthesis Of An Ultrathin Vanadium Dioxide Film On A Flexible Substrate, Preserving Film’s Electrical Properties
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "Strain-free thin film growth of vanadium dioxide deposited on 2D atomic layered material of hexagonal boron nitride investigated by their thickness dependence of insulator–metal transition behavior" was published by researchers at Osaka University and National Institute for Materials Science. Abstract "We report on the preparation of vanadium dioxide (VO2) ul... » read more

RISC-V High Performance Multicore and GPU SoC Platform For Safety Critical System
By Technical Paper Link - 03 Mar, 2025 - Comments: 0

A new technical paper titled "A RISC-V Multicore and GPU SoC Platform with a Qualifiable Software Stack for Safety Critical Systems" published by researchers at Universitat Politecnica de Catalunya and Barcelona Supercomputing Center. Abstract "In the context of the Horizon Europe project, METASAT, a hardware platform was developed as a prototype of future space systems. The platform is bas... » read more

Challenges Grow For Medical ICs
By Gregory Haley - 03 Mar, 2025 - Comments: 0

Demand for medical ICs used inside and outside the body is growing rapidly, but unique manufacturing and functional requirements coupled with low volumes have turned this into a complex and extremely challenging market. Few semiconductor applications demand this level of precision, reliability, and long-term stability. Unlike consumer electronics, where failure might mean a reboot or chip re... » read more

Chip Industry Week In Review
By The SE Staff - 28 Feb, 2025 - Comments: 0

Intel said its new fab in Licking County, Ohio will be delayed due to financial struggles and a need to align chip production with market demand, reported the Columbus Dispatch. Construction is now estimated to be completed in 2030, with operations to start in 2030 or 2031. The company said it already has invested $3.7 billion locally. Apple plans to invest more than $500 billion in the U.S... » read more

The Price Of Fear
By Brian Bailey - 27 Feb, 2025 - Comments: 0

In my last blog, I talked about how pain is important when making predictions in the semiconductor industry. Pain is related to time to market and risk, and the flip side of risk is fear. Fear is one of the main drivers for a large number of EDA tools, such as those related to verification. The fear is taping out a chip, then waiting for what seems like an eternity to get the first chips bac... » read more

Simplifying HW/SW Co-Verification With PSS Led UVM And C Tests
By Todd Burkholder - 27 Feb, 2025 - Comments: 0

By Todd Burkholder, Wael Abdelaziz Mahmoud, Tom Fitzpatrick, Vishal Baskar, and Mohamed Nafea The complexity of system on chips (SoCs) continues to grow rapidly with the integration of more functionality onto a single chip. As a result, traditional verification methodologies struggle to keep pace with the growing complexities, leading to longer development cycles and increased risk of design... » read more

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