Chips Getting More Secure, But Not Quickly Enough


Experts at the Table: Semiconductor Engineering sat down to talk about the impact of heterogeneous integration, more advanced RISC-V designs, and a growing awareness of security threats, with Mike Borza, Synopsys scientist; John Hallman, product manager for trust and security at Siemens EDA; Pete Hardee, group director for product management at Cadence; Paul Karazuba, vice president of marketin... » read more

Solving Memory Mapping Issues with Deep RL (Google)


A technical paper titled "Optimizing Memory Mapping Using Deep Reinforcement Learning" was published by Google DeepMind and Google. Abstract: "Resource scheduling and allocation is a critical component of many high impact systems ranging from congestion control to cloud computing. Finding more optimal solutions to these problems often has significant impact on resource and time savings, red... » read more

EV Charging Hardware Attacks


A technical paper titled "ChargeX: Exploring State Switching Attack on Electric Vehicle Charging Systems" was published by researchers at Michigan State University, Washington University in St. Louis, and Texas A&M University. Abstract: "Electric Vehicle (EV) has become one of the promising solutions to the ever-evolving environmental and energy crisis. The key to the wide adoption of E... » read more

Non-Traditional Design of Dynamic Logic Gates and Circuits with FDSOI FETs


A new technical paper titled "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing" was published by researchers at University of Stuttgart, UC Berkeley, Indian Institute of Technology Kanpur, and TU Munich, with funding by the German Research Foundation. Abstract "In this paper, we propose a non-traditional design of dynamic logic circuits using Fully-Deplet... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits


A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Week In Review: Semiconductor Manufacturing, Test


TECHCET is forecasting semiconductor precursor revenues, both for high-ƙ metal dielectrics and low-ƙ dielectrics, will increase in the second half of 2023, rebounding from the current zero percent growth rate. Wafer start volumes are expected to rebound in 2024 with expansions in 2nm and 3nm logic devices. SEMI also predicts the global slump in semiconductor sales will end this quarter, gi... » read more

Week In Review: Design, Low Power


Design Ansys has signed a definitive agreement to acquire EDA tool company Diakopto. Diakopto specializes in software tools that find the cause of layout parasitics. Its products are ParagonX, for analyzing and debugging IC designs and layout parasitics, and EM/IR analysis/verification tool PrimeX. The deal is expected to close in the second quarter of 2023. SEMI’s FlexTech community issu... » read more

Week In Review: Auto, Security, Pervasive Computing


Former Apple engineer Weibao Wang was indicted for stealing Apple’s autonomous vehicle hardware and software IP and giving the information to Chinese competitors. Among other items, authorities said they found source code for the project on the engineer’s personal laptop, which was seized at his home. Wang fled to China the same day a search warrant was executed. This is one of five cases b... » read more

Etch Processes Push Toward Higher Selectivity, Cost Control


Plasma etching is perhaps the most essential process in semiconductor manufacturing, and possibly the most complex of all fab operations next to photolithography. Nearly half of all fab steps rely on a plasma, an energetic ionized gas, to do their work. Despite ever-shrinking transistor and memory cells, engineers continue to deliver reliable etch processes. “To sustainably create chips... » read more

Challenges Grow For Creating Smaller Bumps For Flip Chips


New bump structures are being developed to enable higher interconnect densities in flip-chip packaging, but they are complex, expensive, and increasingly difficult to manufacture. For products with high pin counts, flip-chip [1] packages have long been a popular choice because they utilize the whole die area for interconnect. The technology has been in use since the 1970s, starting with IBM�... » read more

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