Indium Tungsten Oxide (IWO) Thin-Film Transistors


A new technical paper titled "Thermally Dependent Metastability of Indium-Tungsten-Oxide Thin-Film Transistors" was published by researchers at Rochester Institute of Technology and Corning Research and Development Corporation. Abstract "Indium tungsten oxide (IWO) has been investigated as an oxide semiconductor candidate for next-generation thin-film transistors (TFTs). Bottom-gate TFTs we... » read more

Optimization of the Inter-Chiplet Interconnect And The Chiplet Placement (ETH Zurich, U. of Bologna)


A new technical paper titled "PlaceIT: Placement-based Inter-Chiplet Interconnect Topologies" was published by researchers at ETH Zurich and University of Bologna. Abstract "2.5D integration technology is gaining traction as it copes with the exponentially growing design cost of modern integrated circuits. A crucial part of a 2.5D stacked chip is a low-latency and high-throughput inter-ch... » read more

Research Bits: Feb. 4


High-power diamond transistors Researchers from the University of Glasgow, RMIT University, and Princeton University created a new diamond transistor for high-power electronics that remains switched off by default. The performance of the diamond was improved by coating it in hydrogen atoms followed by layers of aluminum oxide. “The challenge for power electronics is that the design of the... » read more

Chip Industry Technical Paper Roundup: Feb. 4


New technical papers recently added to Semiconductor Engineering’s library: [table id=403 /] Find all technical papers here. » read more

Indium Nitrate As An Advanced Metal-Oxide Resist for EUV Lithography


A new technical paper titled "Sensitivity and contrast of indium nitrate hydrate resist evaluated by low-energy electron beam and extreme ultraviolet exposure" was published by researchers at UT Dallas. "We evaluate the sensitivity and contrast of indium nitrate resists by analyzing dose curves collected using electron beam lithography (EBL) and extreme ultraviolet (EUV) exposure, " states t... » read more

Mixed-Precision DL Inference, Co-Designed With HW Accelerator DPU (Intel)


A new technical paper titled "StruM: Structured Mixed Precision for Efficient Deep Learning Hardware Codesign" was published by Intel. Abstract "In this paper, we propose StruM, a novel structured mixed-precision-based deep learning inference method, co-designed with its associated hardware accelerator (DPU), to address the escalating computational and memory demands of deep learning worklo... » read more

PCIe Over Optics


Moving data through a chip or package, and between packages and systems, is becoming a much bigger challenge as the volume of data continues to explode, and as more compute resources are deployed to work on data-intensive problems such as training AI algorithms or running long and complex simulations. There is more data to process in more places, more levels of data storage and access, and any ... » read more

UCIe For 1.6T Interconnects In Next-Gen I/O Chiplets For AI Data Centers


The rise of generative AI is pushing the limits of computing power and high-speed communication, posing serious challenges as it demands unprecedented workloads and resources. No single design can be optimized for the different classes of models – whether the focus is on compute, memory bandwidth, memory capacity, network bandwidth, latency sensitivity, or scale, all of which are affected by ... » read more

AI In Data Management Has Limits


AI algorithms are being integrated into a growing number of EDA tools to automate different aspects of data management, but they also are forcing discussions about just how much decision-making should be turned over to machines and when that should happen. The ability of AI to sort through enormous amounts of design data to find patterns, both good and bad, is well recognized at this point. ... » read more

Processing-Using-DRAM: Attaining High-Performance Via Dynamic Precision Bit-Serial Arithmetic (ETH Zurich, et al.)


A new technical paper titled "Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic" was published by researchers at ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research. Abstract "Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM structures ... » read more

← Older posts Newer posts →