The When, Why, And How Of Waiting And Backoff In Multi-Threaded Applications On Arm
By Ola Liljedahl - 16 Jan, 2025 - Comments: 0

With multithreaded applications, there are situations where it is unavoidable or desirable to wait for other threads. Implementing such wait instruction sequences correctly is important for both multithreaded scalability and power efficiency. Scalability is measured both in terms of aggregated throughput and fairness. Fairness is when all contending threads get an equal share of the contended ... » read more

Is Liquid Cooling The Future Of Your Data Center?
By Veena Parthan - 16 Jan, 2025 - Comments: 0

The data center industry is facing unprecedented challenges. With chip densities skyrocketing, high-performance computing is being pushed to its limits, all while energy costs are soaring and environmental concerns are escalating. Securing approvals for new data center facilities has become more complex, often plagued by community objections and grid supply issues. However, amidst these hurd... » read more

Power Budgets Optimized By Managing Glitch Power
By Adam Kovac - 16 Jan, 2025 - Comments: 0

“Waste not, want not,” says the old adage, and in general, that’s good advice to live by. But in the realm of chip design, wasting power is a fact of physics. Glitch power – power that gets expended due to delays in gates and/or wires – can account for up to 40% of the power budget in advanced applications like data center servers. Even in less high-powered circuits, such as those fou... » read more

Tame IR Drop Like Google
By Jeff Wilson - 16 Jan, 2025 - Comments: 0

In the relentless pursuit of semiconductor performance and efficiency, tech giants like Google are constantly pushing the boundaries of what's possible. As they scale their designs to the cutting-edge 3nm node, power integrity has emerged as a critical challenge that must be overcome. Enter Calibre DesignEnhancer (DE), Siemens' analysis-based solution for enhancing design reliability and man... » read more

2025: So Many Possibilities
By Brian Bailey - 16 Jan, 2025 - Comments: 0

The stage is set for a year of innovation in the chip industry, unlike anything seen for decades, but what makes this period of advancement truly unique is the need to focus on physics and real design skills. Planar scaling of SoCs enabled design and verification tools and methodologies to mature on a relatively linear path, but the last few years have created an environment for more radical... » read more

What’s The Best Way To Sell An Inference Engine?
By Bryon Moyer - 16 Jan, 2025 - Comments: 0

The burgeoning AI market has seen innumerable startups funded on the strength of their ideas about building faster, lower-power, and/or lower-cost AI inference engines. Part of the go-to-market dynamic has involved deciding whether to offer a chip or IP — with some newcomers pivoting between chip and IP implementations of their ideas. The fact that some companies choose to sell chips while... » read more

Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper/mini-review titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by researchers at TSMC and National Tsing Hua University. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devi... » read more

Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation" was published by researchers at NVIDIA Research. Abstract: "Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, ... » read more

Domain Wall Fluctuations in Sliding Ferroelectrics (Cambridge, Argonne)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "Superconductivity from Domain Wall Fluctuations in Sliding Ferroelectrics" was published by researchers at University of Cambridge and Argonne National Lab. Abstract: "Bilayers of two-dimensional van der Waals materials that lack an inversion center can show a novel form of ferroelectricity, where certain stacking arrangements of the two layers lead to an inter... » read more

Transformation Of Polarons As Tellurene Becomes Thinner
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new research paper titled "Thickness-dependent polaron crossover in tellurene" was published by researchers from Rice University, Lawrence Berkeley National Laboratory, MIT, Argonne National Laboratory, ORNL, Purdue University, and Stanford University. Abstract "Polarons, quasiparticles from electron-phonon coupling, are crucial for material properties including high-temperature supercond... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy