Globally Asynchronous, Locally Synchronous Clocks
By Ed Sperling - 04 Nov, 2024 - Comments: 0

Typical IC clocking schemes are under stress in complex chip/chiplet designs, where multiple compute elements may not be operating at the same frequency consistently. Some cores may be powered down to save energy, or they may age at different rates, which in turn reduces performance. Lee Vick, vice president of strategic marketing at Movellus, explains why locally asynchronous clocking schemes ... » read more

Managing Reflections With Terminations
By John Golding - 04 Nov, 2024 - Comments: 0

Have you heard recommendations to use a particular termination in particular situations for good signal integrity? Have you ever wondered how to incorporate terminations in your design? While there are typical use cases for various terminations, sometimes engineers use termination techniques based on a recommendation or assumption that may not work, or at least may not be optimal, for their par... » read more

EMEA Investments Driving Technology Specialization
By Liz Allan - 04 Nov, 2024 - Comments: 0

Government programs across Europe and the UK are seeing a surge of investments in leading edge technology, materials, and packaging. Industry and academia are coalescing around specialty areas, drawing on established relationships to foster innovation and fill gaps in regional supply chains while also maintaining international bonds. Government initiatives also are picking up in Israel, Saudi A... » read more

Chip Industry Week In Review
By The SE Staff - 01 Nov, 2024 - Comments: 0

Siemens announced plans to acquire Altair Engineering, a provider of industrial simulation and analysis, data science, and high-performance computing (HPC) software, for about $10 billion. Altair's software will become part of Siemens' Xcelerator portfolio and provide a boost to physics-based digital twins. Onto Innovation bought Lumina Instruments, a San Jose, California-based maker of lase... » read more

Why 40G UCIe IP?
By Aparna Tarde - 31 Oct, 2024 - Comments: 0

AI applications are bringing new challenges to the semiconductor industry. There is an increased demand for greater bandwidth, especially for compute and networking applications to support the high data processing required by deep learning and machine learning algorithms. The requirements for these AI applications are different for die-to-die interfaces. Let’s take 100Tb networking switches a... » read more

Reducing SoC Power With NoCs And Caches
By Andy Nightingale - 31 Oct, 2024 - Comments: 0

Today’s system-on-chip (SoC) designs face significant challenges with respect to managing and minimizing power consumption while maintaining high performance and scalability. Network-on-chip (NoC) interconnects coupled with innovative cache memories can address these competing requirements. Traditional NoCs SoCs consist of IP blocks that need to be connected. Early SoCs used bus-based archi... » read more

Chiplets Make Progress Using Interconnects As Glue
By Ann Mutschler - 31 Oct, 2024 - Comments: 0

Breaking up SoCs into their component parts and putting those and other pieces together in some type of heterogeneous assembly is beginning to take shape, fueled by advances in interconnects, complex partitioning, and industry learnings about what works and what doesn't. While the vision of plug-and-play remains intact, getting there is a lot more complicated than initially imagined. It can ... » read more

Revolutionizing High-Performance Silicon With Next-Gen Chiplets
By Shivi Arora - 31 Oct, 2024 - Comments: 0

By Shivi Arora and Sue Hung Fung As 5G wireless communications systems continue to be deployed, enterprises are busy planning for 6G—the next generation of wireless communications set to transform our lives. Poised to merge communication and computing, 6G promises to create a hyperconnected world that blends digital and physical experiences with ultra-fast speeds and low latency as a start... » read more

HW and SW Architecture Approaches For Running AI Models
By Karen Heyman - 31 Oct, 2024 - Comments: 0

How best to run AI inference models is a current topic of much debate as a wide breadth of systems companies look to add AI to a variety of systems, spurring both hardware innovation and the need to revamp models. Hardware developers are making progress with AI accelerators and SoCs. But on the model side, questions abound about whether the answer might come from revisiting older, less compl... » read more

Locking When Emulating Xtensa LX Multi-Core On A Xilinx FPGA
By Nayan Gaywala - 31 Oct, 2024 - Comments: 0

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environme... » read more

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