The Cost Of EDA Data Storage And Processing Efficiency


Engineering teams are turning to the cloud to process and store increasing amounts of EDA data, but while the compute resources in hyperscale data centers are virtually unlimited, the move can add costs, slow access to data, and raise new concerns about sustainability. For complex chip designs, the elasticity of the cloud is a huge bonus. With advanced-node chips and packaging, the amount of... » read more

Blog Review: Oct. 9


Siemens’ Stephen Chavez looks at the key benefits and challenges to achieving a successful ECAD-MCAD collaboration. Cadence’s Nayan Gaywala shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform, using a dual-core design mapped to a KC705 platform as an example. Synopsys’ Vincent van der Leest digs into SRAM PUFs and their ... » read more

High-NA EUV Lithography: Enhancing Resolution By Split Pupil Exposure (Fraunhofer, ASML)


A new technical paper titled "Resolution enhancement for high-numerical aperture extreme ultraviolet lithography by split pupil exposures: a modeling perspective" was published by researchers at Fraunhofer IISB and ASML. The open source paper published on SPIE states: "The lithographic imaging performance of extreme ultraviolet (EUV) lithography is limited by the efficiency of light diffrac... » read more

Research Bits: Oct. 8


Soft, flexible polymer semiconductors Stanford University materials scientists used a specialized electron microscope – cryo-electron microscopy (Cryo 4D-STEM) – to explore the microstructure of soft semiconductors that could lead to new-generation electronics. Organic mixed ionic-electronic conductors (OMIECs) are soft, flexible polymer semiconductors with promising electrochemical qua... » read more

Chip Industry Technical Paper Roundup: Oct. 8


New technical papers recently added to Semiconductor Engineering’s library: [table id=365 /] More ReadingTechnical Paper Library home » read more

EDA And IP Revenue Grow, But Markets Are Shifting


EDA and IP revenue grew 18.2% worldwide to $4.69 billion in Q2, year-over-year, with all product categories and regions reporting increases, but a drill down into the numbers shows some new pockets of growth and weakness The Asia/Pacific region exhibited strong growth once again, but the dynamics in that market have changed significantly. China is no longer the primary revenue generator for ... » read more

Strain Engineering in 2D FETs (UCSB)


A new technical paper titled "Strain engineering in 2D FETs: Physics, status, and prospects" was published by researchers at UC Santa Barbara. "In this work, we explore the physics and evaluate the merits of strain engineering in two-dimensional van der Waals semiconductor-based FETs (field-effect-transistors) using DFT (density functional theory) to determine the modulation of the channel m... » read more

TFETs: Design and Operation, Including Material Selection and Simulation Methods


A new technical paper titled "Multiscale Simulation and Machine Learning Facilitated Design of Two-Dimensional Nanomaterials-Based Tunnel Field-Effect Transistors: A Review" was published by researchers at University of Chicago and Argonne National Lab. Abstract "Traditional transistors based on complementary metal-oxide-semiconductor (CMOS) and metal-oxide-semiconductor field-effect transi... » read more

Government Chip Funding Spreads Globally


This is the first in a series of articles tracking government chip investments. See part two for Americas-focused funding and part three for the UK and EMEA, and part four for Asia. Countries around the world are ramping up investments into their semiconductor industries as part of new or existing approaches. The increased government activity stems from growing awareness of the strategic imp... » read more

Multi-Node, Virtualized Neuromorphic Architecture


A new technical paper titled "NeuroVM: Dynamic Neuromorphic Hardware Virtualization" was published by researchers at Stanford University, UT Austin and Temsa Research & Development Center. Abstract "This paper introduces a novel approach in neuromorphic computing, integrating heterogeneous hardware nodes into a unified, massively parallel architecture. Our system transcends traditional ... » read more

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