Scaling AI Infrastructure: The Critical Role Of PCIe 7.0 Retimers
By Lou Ternullo - 13 Nov, 2025 - Comments: 0

In a previous blog, Scaling in the AI Era: The Role of PCI Express 7.0 Switches in Next-Gen Data Centers, we explored how PCIe 7.0 switches enable high-bandwidth, low-latency interconnects for AI-driven data centers. Switches are essential for building flexible, composable architectures that connect thousands of GPUs, accelerators, and memory subsystems. But as AI clusters grow in size and comp... » read more

Power Integrity And Voltage Issues Get Harder To Detect And Solve
By Ann Mutschler - 13 Nov, 2025 - Comments: 0

Voltage and power integrity are becoming increasingly critical and challenging for chip designers and architects, regardless of which process technology they are using or which market they are targeting. An explosion of features vying unevenly for current is increasing the number of constraints and possible interactions that engineers need to sort through to ensure reliability. These include... » read more

Accellera Standard Supports Hierarchical Data Model For CDC And RDC Analysis
By Farhad Ahmed - 13 Nov, 2025 - Comments: 0

The hierarchical flow for clock domain crossing (CDC) and reset domain crossing (RDC) is a methodology used in the verification of large, complex digital integrated circuits. It's a divide-and-conquer approach that significantly improves the efficiency and turnaround time for ensuring design reliability against metastability and other issues at asynchronous boundaries. Questa CDC and RDC sol... » read more

Predictable Design Optimization And Closure With Adaptive Scenario Compression
By James Chuang - 13 Nov, 2025 - Comments: 0

Modern semiconductor chip design faces growing complexity due to numerous timing scenarios driven by varying operating conditions and physical effects. This complexity is especially pronounced in mobile and automotive chips, which require optimization across diverse performance and reliability demands. Designers currently focus on a limited subset of scenarios to manage computational load, but ... » read more

Future Architecture Technologies: POE2 And vMTE
By Martin Weidmann - 13 Nov, 2025 - Comments: 0

Future Architecture Technologies are features being developed for currently unreleased versions of the Arm architecture. Arm provides the ecosystem with relevant information and specifications in advance, ensuring software support for when new technologies are realized in hardware. This blog introduces two future technologies: Permission Overlay Extension version 2 (POE2), and Virtual T... » read more

Multiple AI Scale-Up Options Emerge
By Bryon Moyer - 13 Nov, 2025 - Comments: 0

Artificial intelligence (AI) workloads are very different from those traditionally run inside of data centers, and while the current infrastructure can accommodate those needs, there is a constant demand for higher performance and better power efficiency. It can take months to train a large language model, even with a huge number of processing elements. Typically this involves commandeering ... » read more

PCIe Low-Power Validation Challenges And Potential Solutions
By Kunal Chhabriya - 13 Nov, 2025 - Comments: 0

As chip complexities increase and the industry evolves to more battery-powered devices, power-aware/consumption research becomes an integral part of design in the industry. Low power is crucial in ASIC applications to ensure longevity, durability, and reliability. PCI-SIG has focused on reducing power consumption while the PCIe interface is active to enable better platform power management (... » read more

The Future Of Digital Engineering In The Age Of AI
By Laura Carter - 13 Nov, 2025 - Comments: 0

Digital engineering gives innovators creative agency to test the limits of their ideas in a virtual environment. It is in this convergence of digital technologies, data-driven models, and advanced simulations where new designs are born at unprecedented levels of speed and accuracy. Adding artificial intelligence (AI) into the mix further accelerates innovation by unlocking opportunities to a... » read more

Parallel Implementation Of Nonlinear Functions Using An Optical Processor (UCLA)
By Technical Paper Link - 12 Nov, 2025 - Comments: 0

A new technical paper titled "Massively parallel and universal approximation of nonlinear functions using diffractive processors" was published by researchers at UCLA. Abstract "Nonlinear computation is essential for a wide range of information processing tasks, yet implementing nonlinear functions using optical systems remains a challenge due to the weak and power-intensive nature of optic... » read more

Improving IC System Quality And Performance
By Ed Sperling - 12 Nov, 2025 - Comments: 0

Ensuring that multi-die assemblies and advanced SoCs will work as expected from time zero to the end of their lifecycle adds new challenges for chipmakers and their customers. Chips are being run harder, hotter, and for longer periods of time, often in unique configurations and with customized workloads. Alex Burlak, vice president of test and analytics at proteanTecs, talks about how to identi... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2026 SMG   |  Terms of Service  |  Privacy Policy