Building A Better Customized Debug And Trace Solution For Multi-Core SoCs

If you think of debug as solving a murder case through the use of backward reasoning, then trace is the video surveillance that helps pinpoint the culprit. Trace is invaluable as it provides real-time visibility into errors, and dramatically cuts down on design cycles and iterations.

A recent study done by Cambridge University found that the global cost of software debugging has risen to the sum of $312 billion dollars per year and that developers spend an average of 50% of their programming time finding and fixing bugs. Divide that massive sum by 7.1 billion people on the planet and it works out to $44 per person – or put another way, it’s enough to buy everyone in the world a Raspberry Pi.

The trend for increasing complexity in SoC designs means that this problem will require more resources in terms of time and money going forward. It is an issue that has given SoC architects and system developer headaches for years.

ITRS 2007 SoC Consumer Portable Design Complexity Trends

This famous quote by President Dwight D. Eisenhower “No battle was ever won according to plan, but no battle was ever won without one,” rings true in the context of debug subsystem design. Understanding debug and trace hardware features and capabilities is critical to building a solution that will meet specific requirements.

A well thought out debug and trace solution can help manage increased complexity by providing the right hardware visibility and hooks. Software developers can use this key functionality to develop optimized software in a timely manner, and with reduced risk of bugs.

Typical use cases should be addressed with a customized debug and trace solution that allows for the following:

• Faster SoC bring-up;
• Easy and quick software debug;
• In-field analysis and postmortem debug, and
• System optimization via profiling, event synchronization.

Debug and Trace Use in SoC Development

The recently introduced ARM CoreSight SoC-400 is a comprehensive solution allowing SoC architects the ability to tailor their designs and meet specific requirements such as:

• Designing for large systems with multiple cores through use of configurable components;
• Maximize debug visibility using a combination of debug components;
• Use IPXACT descriptors for all components to automate stitching and for test bench generation;
• Support different trace bandwidth requirements for complex SoCs;
• Accelerate design and verification through example subsystems, testbenches, test cases and necessary verification IP components, and
• Support multiple hardware debug models for multiple use cases.

When put into a wider context, design teams can have a real advantage reducing design development and software debug cycles significantly, and use trace to efficiently identify errors to reduce design cycles and iterations. This should help cut down on that $312 billion dollar global debug bill.

For more information, download a new white paper that outlines the steps to building a debug and trace solution, along with design and verification flow recommendations. You can also view an on-demand webinar on the subject to learn more.