Can IP Be Standardized In Low-Power Designs?

At this point there’s a lot more than what’s in the standards, but at least it’s a starting point.

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By Ann Steffora Mutschler

SoC designers are beginning to embrace low power formats UPF (IEEE P1801) and the Common Power Format (CPF) to express power intent, but are these efforts enough to create standardized IP in low power designs?

Mike Brogley, IP and solutions product marketing manager at Actel, believes it is possible. “Yes, IP can be standardized, but the main driver in low-power applications is really the device, not any particular circuit implementation.”

“Power-aware design is very important. Design practices like power-aware clock domain management are critical to the management of power in battery operation handheld device applications, and use of flexible sleep modes that retain data and circuitry states can yield major advances in battery life,” he said, but he cautioned that flash-based FPGAs, for example, can deliver such radically lower power consumption compared to SRAM-based FPGA devices that the selection of the “theoretical best vs. absolute worst design practices for power consumption would yield nothing close to the differences between the underlying device technologies.”

Brogley said IEEE P1801 (UPF) “certainly brings a lot to the table—a standardized way of describing power across the design spectrum cannot be undervalued. The degree to which tools providers support the UPF language and methodology in the tools applicable to FPGA design will drive the relevance to IP in the FPGA world.

Looking at it from a higher level, Ken Brock, director of physical IP marketing at Virage Logic said the standards efforts “take care of the needs of the EDA vendors, which is a very important component of the recipe. [But] it doesn’t really address a lot of the other issues for IP vendors. It doesn’t address which voltages, which temperatures are across the line, and certainly doesn’t address any of the functionality issues.”

Vic Kulkarni, senior VP and GM of the RTL business unit at Apache Design Solutions, agrees with Brock. “There is more to it than just the CPF or UPF standards—that’s really the key,” and points out the importance of understanding the bigger drivers at play. It requires looking at the technology migrations and technology advancements to put things into perspective.

Starting with timing, signal integrity was the key, he noted, followed by static IR. Dynamic power issues took over at 65nm as interconnect-driven timing became more critical, which impacted the RC as opposed to the pure timer. Then reliability came into the picture at 45nm with intra-domain challenges to cross-domain challenges; a domain defined as creating an IP, putting the IP in the context of an SoC, with that SoC put into the context of a PCB and package. In terms of creation of IP, it could be digital IP or analog to digital, then the I/Os come in the picture. How do you manage these extremely high speed DDRs? DDRs are pretty much driving the apps we just talked about, he said.

“CPF or UPF is very critical as part of driving a low power intent, but that’s not good enough for sign-off and assuring that indeed your IP works in the context of SoC and package,” Kulkarni explained. He said Apache looks at this issue holistically in terms of creation of IP at the ESL world, the RTL world, the logic world and then the process world and bringing all of them together.

“If you look at what happens to power, if you target it early in the design, you have the highest probability of making an impact on the creation of low-power or low-noise-aware IP and SoCs. You have to target at the higher levels of abstraction but as you go down toward synthesis and post-place & route, the ability to impact power gets further and further reduced. However, by the same definition the implementation and signoff importance increases because they have to be more and more precise toward the silicon. So combining these two is critical in terms of IP creation and IP validation. Mitigating power integrity issues from power reduction techniques happens in the implementation phase,” Kulkarni said.

“UPF and CPF are about low power intent and that is required only for extremely high-level designers, but once you get down in the RTL what do you do with it? It keeps you ‘low-power correct’ in terms of specifying islands that are created but if those island start switching, what happens to my physical design? That they can’t tell you,” he added.

While UPF and CPF are a great start, it may be a few more years before it is truly possible to standardize IP in low power designs given the use cases it needs to be characterized for.