The Coming NPU Population Collapse


At some point in everyone’s teenage years of schooling we were all taught in a nature or biology class about cycles of population surges and then inevitable population collapses. Whether the example was an animal, plant, insect or even bacteria, some external event triggers a rapid surge in the population of a species which leads to overpopulation and competition for resources (food, space, s... » read more

Industry Leaders Provide Insights And Guidance On Multi-Die Designs


Multi-die designs seamlessly integrate multiple heterogeneous or homogeneous dies in a single package to significantly enhance chip performance and efficiency — making them indispensable for high-performance computing (HPC), artificial intelligence (AI), data analytics, advanced graphics processing, and other demanding applications. While representing a groundbreaking leap forward, multi-d... » read more

Model-Based Systems Engineering


Today’s electronic systems are an increasingly complex combination of hardware and software components. They contain an ever-expanding range of functions, require more computing power, have to operate a wide variety of interfaces, comply with standards, and be compatible with established market solutions. Accommodating all the new functions and expanded capacity may require a larger silicon a... » read more

Smarter, Faster, Leaner: Rethinking Verification For The Modern Era


Verification isn’t just another step in the semiconductor design process—it’s increasingly the step that defines whether teams hit their schedules or miss the mark. With skyrocketing design complexity, accelerated development timelines, and persistent engineering shortages, the industry is feeling the pressure. Traditional methods aren’t keeping pace. At Siemens, we’ve been rethink... » read more

Meeting The Performance Demands Of The Next-Gen Client PC Market


The client PC market is undergoing a transformative shift. As AI becomes a cornerstone of modern computing, the architecture of client systems—particularly notebooks and desktops—is being reimagined to support the immense data processing needs of these workloads. From real-time inferencing to generative applications, AI is redefining what performance means in a personal computer. With th... » read more

Introducing GICv5: Scalable And Secure Interrupt Management For Arm


As Arm-based infrastructure continues to scale across markets, demands on system components increase. This can mean more interrupts, or signals from hardware/software to a processor to pause a task and handle another. Arm’s Generic Interrupt Controller Architecture (GIC) helps manage the communication between devices and processors efficiently. It makes sure the right processor handles the r... » read more

Simplify Simulation With Reduced-Order Modeling


One of the biggest challenges in engineering and design is striking a balance between accuracy and speed. Development teams strive for precision but must often accelerate their simulation and computational workflows to meet production demands. Although physics-based, high-fidelity simulations are highly accurate, they are computationally expensive in terms of time and resources due to their com... » read more

Verification Software And Methodology Insights


Earlier this month, I had the opportunity to attend CadenceLIVE Silicon Valley 2025. Among the many engaging sessions, the Verification Software track highlighted how leading companies are advancing verification methodologies to meet the demands of increasingly complex designs. The track featured seven presentations from industry leaders, each offering a unique perspective on how SVG’s verif... » read more

Optimizing Analog With Layout In The Loop


Meeting high-performance requirements at low power isn’t easy. What is already challenging in digital is even more complex in analog. After specification and block-level system concept, the analog design flow typically spends considerable time coming up with well-working schematic-level topologies. However, once layout parasitics become apparent through parasitic extraction, the seemingly opt... » read more

Best Practices For Power-Aware Verification: Because Designing For Low Power Is Only Half The Battle


As modern chips push the limits of power efficiency, power management has become a top priority. With today’s increasingly complex devices, verifying power intent isn’t just a technical requirement. It’s a necessity for building reliable silicon. One of the most important lessons learned in recent years is that RTL and power intent must evolve together. Treating power intent as a post... » read more

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