category: Blogs – LPHP

category: Auto, Security & Edge AI

Rethinking Ethernet For The AI Scale-Up Era: Inside ESUN
By Abhinav Kothiala - 13 Jul, 2026 - Comments: 0

Every generation of AI infrastructure has redefined what "the network" means. In today's training clusters — scaling from hundreds to hundreds of thousands of accelerators — the interconnect is no longer a supporting actor. It has become a first-order determinant of system throughput, utilization, and cost per token. Accelerators inside these systems don't just move data; they synchronize o... » read more

The Architecture Decisions Behind A Production-Ready EDA AI Agent
By Emma-Jane Crozier - 09 Jul, 2026 - Comments: 0

The conversation about agentic AI in semiconductor and PCB design tends to focus on capability: what the agent can do, how much time it saves, and which parts of the workflow it can automate. That is a reasonable place to start, but that is not where the hard engineering happens. Organizations are now asking whether AI agents can take on meaningful portions of the workflow, not as assistants th... » read more

The Expansion Of LPDDR Into Edge AI Platforms
By Paul Karazuba - 09 Jul, 2026 - Comments: 0

As artificial intelligence continues its migration from centralized data centers to distributed systems, one reality is becoming unmistakable: the future of AI is increasingly defined at the edge. Whether embedded in smart cameras, industrial controllers, or next-generation vehicles, AI is no longer confined to racks of GPUs. It is operating in power-constrained, thermally limited, and space-re... » read more

UALink Under The Hood: Why Full-Stack Verification Wins
By Sandeep Grover - 09 Jul, 2026 - Comments: 0

It is tempting to picture UALink as a clean line between two accelerators: requests enter one side, responses emerge from the other. The abstraction is useful — but it conceals almost everything that makes the protocol interesting, and almost everything that makes it difficult to verify. Verifying UALink means following a transaction the way the silicon does: down through four layers, out ... » read more

From Host Node To Heterogeneous Rack: Rethinking The AI CPU
By Satadal Bhattacharjee - 09 Jul, 2026 - Comments: 0

AI infrastructure is entering a crucial new phase. The first phase of generative AI infrastructure was defined by accelerator scale: how many GPUs, NPUs or custom AI accelerators could be deployed, powered, cooled and connected. That phase is not over, but it is no longer sufficient. The next phase is about rack-scale system composition: heterogeneous AI racks where different compute resourc... » read more

Benchmarking An NPU At Scale
By Marc Meszaros - 09 Jul, 2026 - Comments: 0

With every Chimera SDK release, something quietly industrial happens: the entire 300+ model zoo gets automatically recompiled and re-profiled across a broad sweep of hardware configurations and the results land in DevStudio in the process. No one is hand-typing FPS numbers into a slide or running a single model on a single configuration to cherry-pick for a datasheet. The whole zoo moves forwar... » read more

Cloud HPC For AI: Addressing Latency, Cost, And Scale At The Architectural Level
By Sumit Vishwakarma - 22 Jun, 2026 - Comments: 0

Many organizations assume that moving HPC workloads to the cloud is simply a matter of lifting and shifting on-premises clusters. In practice, that approach often erodes performance, inflates costs, and undermines AI training efficiency. Getting the most out of HPC in the cloud requires a fundamentally different architectural approach — one that minimizes latency, maximizes utilization, an... » read more

Mastering 3D-IC Verification Complexity
By Matt Grange - 11 Jun, 2026 - Comments: 0

The semiconductor industry's transition from traditional 2D integrated circuits to 2.5D and 3D-IC configurations represents more than an incremental advancement. This architectural shift, driven by the need to push beyond conventional scaling limitations, introduces a cascade of verification challenges that legacy methodologies struggle to address. As designs incorporate multiple stacked dies, ... » read more

Clocked DDR5 Client Memory Modules Enable Scaling To 9600 MT/s For AI PCs
By Carlos Weissenberg - 11 Jun, 2026 - Comments: 0

AI PCs are driving a new class of client workloads that behave very differently from traditional productivity or multimedia applications. Agentic AI systems are expected to plan, execute, and adapt in real time, maintaining persistent context while orchestrating multiple concurrent tasks. These usage patterns place sustained pressure on the memory subsystem, requiring not only higher peak bandw... » read more

How To Start Building Edge-Native AI
By Sharad Chole - 11 Jun, 2026 - Comments: 0

Cloud AI enables features like voice assistants and recommendations via centralized data centers, but it relies on consistent network connectivity, which often fails in real-world conditions. Edge-native AI shifts inference to devices such as phones, cars, and sensors, enabling real-time processing, enhanced privacy, and operational resilience. Why edge AI outpaces cloud Edge AI addresses key... » read more

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