Power Integrity Without Blind Spots: A System Level Approach To 3D-ICs


Power delivery has become one of the defining challenges of next-generation semiconductor systems. As AI, high-performance computing, and data-centric workloads drive higher performance and tighter integration, traditional 2D SoC design approaches are reaching their limits. The industry’s shift toward 2.5D and 3D heterogeneous integration promises breakthroughs in performance and efficiency�... » read more

Rethinking Robotics Reinforcement Learning: A Practical Humanoid Training Workflow


Reinforcement learning (RL) for robotics is often associated with large GPU clusters, distributed infrastructure, and x86-based development environments. Training a humanoid robot with high-fidelity simulation is a resource-intensive workflow that runs in the data center. What if that workflow could run on a single workstation? In this blog post, we explore a complete robotics pipeline bu... » read more

Redefining AI Inference With New Silicon Architecture


AI inference is rapidly becoming the largest and most demanding segment of the AI market, but the cost of running these workloads continues to be a major challenge. VSORA, a fabless semiconductor company, is tackling this problem head-on with a fresh approach to high‑performance AI processing and a deep collaboration with Cadence. VSORA develops advanced AI chips that dramatically reduce t... » read more

HBM4E Raises The Bar For AI Memory Bandwidth


The pace of AI innovation continues to expose a painful reality. Compute keeps scaling, but memory bandwidth remains one of the hardest bottlenecks to remove. As AI models grow larger and more complex, feeding data fast enough into accelerators has become just as critical as raw compute capability. High Bandwidth Memory (HBM) has been central to solving this challenge, and the next step in that... » read more

Human-Centered Agentic AI Comes To RTL Verification


For decades, productivity gains in electronic design automation (EDA) came from better engines. Faster solvers, higher-capacity simulators, and more scalable formal tools allowed design and verification teams to keep pace as designs grew larger. That model is no longer sufficient. Today’s design and verification bottleneck is not raw tool performance, but the coordination overhead required... » read more

Rethinking Voice AI At The Edge: A Practical Offline Pipeline


Cloud-based AI dominates the headlines, but responsive and private interaction lies at the edge. This blog post shows how to build a fully offline, real-time voice assistant using the Arm-based NVIDIA DGX Spark platform. The system integrates open-source components such as faster-whisper and vLLM. It delivers low-latency, human-like dialogue without sending data outside the local environment. ... » read more

Serial Wire Debug (SWD) Protocol: Efficient Debug Interface For Arm-Based Systems


Modern embedded systems are becoming increasingly compact, power efficient, and feature rich. As SoCs integrate more functionality, developers need reliable debug access without increasing pin count or board complexity. Serial Wire Debug (SWD) addresses these needs by providing a streamlined alternative to JTAG, enabling high performance debug features using only two pins, making it ideal for t... » read more

Customizing Foundation IP For Ultra-Low-Voltage Designs


By Daryl Seitzer, Andrew Appleby, and Mohammad Tanveer Building a new system-on-chip (SoC) starts with assembling the right foundational elements—pre‑verified IP for logic, memory, I/O, and other essential functions. Standard IP solutions typically address most common design needs, but some projects call for more specialized approaches, especially when innovation is critical or when t... » read more

The On-Device LLM Revolution


The AI world is experiencing a fundamental shift. After years of cloud-centric inference dominated by massive data center GPUs, we're witnessing an accelerating migration of language models to edge devices. These are not the trillion-parameter behemoths that require server farms, but the "Goldilocks zone" models: 3B to 30B parameters — large enough to deliver genuinely useful AI capabilities,... » read more

AI Inference Needs A Mix-And-Match Memory Strategy


AI inference is no longer a single workload that can be served efficiently by a single type of accelerator or memory. From fast chat replies to 10M token codebases, inference spans wildly diverse workloads with very different limits on latency, bandwidth, capacity, and compute, as the figure below demonstrates.1 Source: Meta1 The AI inference spectrum of workloads includes: Inter... » read more

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