Scaling Server Memory Performance To Meet The Demands Of AI


AI, whether we’re talking about the number of parameters used in training or the size of large language models (LLMs), continues to grow at a breathtaking rate. For over a decade, we’ve witnessed a 10X per year scaling. It’s a growth rate that puts pressure on every aspect of the computing stack: processing, memory, networking, you name it. The platform vendors are responding to the in... » read more

SoC Telemetry & Performance Analysis Using Statistical Profiling Extension


The Arm Statistical Profiling Extension (SPE) is an architectural feature designed for enhanced instruction execution profiling within Arm CPUs. This feature has been available since the introduction of the Neoverse N1 CPU platform in 2019, along with performance monitor units (PMUs) generally available in Arm CPUs. An important step in extracting value from capabilities like SPE and PMUs is th... » read more

Multi-Chiplet Marvels: Exploring Chip-Centric Thermal Analysis


The relationship between power consumption and thermal dynamics for chips is intricate. As power is consumed during the operation of a chip, it results in the generation of heat. This heat may dissipate from the device, metal routing, or the die itself, leading to increased temperatures on the chip. The dissipation process perpetually expends redundant energy, thereby compromising on the overal... » read more

Exploring The Facets Of Stray Light With Simulation


Seems like everywhere you look, there’s someone snapping a memorable group photo or perfect selfie with their phones. As the line between traditional and cellphone cameras continues to blur, manufacturers of these handheld devices are pressed to find the best combination of software and hardware to achieve image quality that was previously unthinkable. Of course, mobile photography has com... » read more

Getting Optimal PPA For HPC & AI Applications With Foundation IP


By Andrew Appleby, Xiaorui Hu, and Bhavana Chaurasia The demand for application-specific system-on-chips (SoCs) for compute applications is ever-increasing. Today, the diversity of requirements means there is a need for a rich set of compute solutions in a wide range of process technologies. The resulting products may have very different but demanding power, performance, and area (PPA) requi... » read more

AI-Driven Macro Placement Boosts PPA


In the era of EDA 4.0, artificial intelligence (AI) and machine learning (ML) are transforming what electronic design automation tools are capable of. For many of the challenges of physical IC design, AI can provide significant benefits to both the turnaround time and the quality of the design, as measured by performance, power, and area (PPA) metrics. One implementation step due for improve... » read more

BYO NPU Benchmarks


In our last blog post, we highlighted the ways that NPU vendors can shade the truth about performance on benchmark networks such that comparing common performance scores such as “Resnet50 Inferences / Second” can be a futile exercise. But there is a straight-forward, low-investment method for an IP evaluator to short-circuit all the vendor shenanigans and get a solid apples-to-apples result... » read more

The Journey To Exascale Computing And Beyond


High performance computing witnessed one of its most ambitious leaps forward with the development of the US supercomputer “Frontier.” As Scott Atchley from Oak Ridge National Laboratory discussed at Supercomputing 23 (SC23) in Denver last month, the Frontier had the ambitious goal of achieving performance levels 1000 times higher than the petascale systems that preceded it, while also stayi... » read more

Requirements For The Efficient Implementation Of AI Solutions On Edge Devices


By André Schneider, Olaf Enge-Rosenblatt, and Björn Zeugmann In recent years, there has been a growing tendency to implement data-driven approaches for the continuous monitoring of industrial plants as part of digitalization and Industry 4.0 initiatives. The hope is to detect critical conditions at an early stage, minimize maintenance and downtimes, and continuously achieve high product qu... » read more

Advanced Design Debug Demands Integrated Verification Management


Design verification has been the dominant portion of chip development for years, and the challenges grow bigger every day. Single dies continue to grow in transistor count and complexity. Advanced techniques such as 2.5D and 3D multi-die systems and emerging technologies such as wafer-scale integration pack even more transistors and functionality into a single device. This situation has created... » read more

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