category: A Bit About Memory

category: IoT, Security & Automotive

CXL: Sorting Out The Interconnect Soup
By Tim Messegee - 11 Feb, 2021 - Comments: 0

In the webinar Hidden Signals: Memory and Interconnect Decisions for AI, IoT and 5G, Shane Rau of IDC and Rambus Fellow Steven Woo discussed how interconnects were a critical enabling technology for future computing platforms. One of the major complications was the “interconnect soup” of numerous and divergent interface protocols. The Compute Express Link (CXL) standard offers to sort out m... » read more

Five Key Changes Coming With DDR5 DIMMs
By John Eble - 14 Jan, 2021 - Comments: 0

On July 14th of last year, JEDEC announced the publication of the DDR5 SDRAM standard. This signaled the nearing industry transition to DDR5 server dual-inline memory modules (DIMM). DDR5 memory brings a number of key enhancements that will bring great performance and power benefits in next generation servers. Scaling Data Rates to 6.4 Gb/s You can never have enough memory bandwidth, and DD... » read more

Pushing The Envelope With HBM2E Memory
By Joseph Rodriguez - 10 Dec, 2020 - Comments: 0

In September, Rambus announced the achievement of reaching 4 gigabits per second (Gbps) operation with our HBM2E memory interface. This milestone was demonstrated in silicon and required mastering substantial signal integrity and power integrity (SI/PI) challenges. The 4 Gbps mark represents a 20% rise from the previous maximum data rate of 3.2 Gbps for HBM2E. To date, the industry’s faste... » read more

The Expanding Universe Of MIPI Applications
By Joseph Rodriguez - 12 Nov, 2020 - Comments: 0

It’s hard to imagine today, but there was a time when mobile phones had no cameras and displays were tiny monochrome LCDs capable of displaying a phone number and not much more. The iconic Nokia 3310 announced Sept. 1, 2000, had an 84 x 48 pixel monochrome display and went on to sell 126 million units worldwide. You may still have one in your junk drawer. By the time of the original iPhone... » read more

GDDR6 Memory For Life On The Edge
By Frank Ferro - 15 Oct, 2020 - Comments: 0

With the torrid growth in data traffic, it is unsurprising that the number of hyperscale data centers has grown apace. According to analysts at the Synergy Research Group, in July of this year there were 541 hyperscale data centers worldwide. That represents a doubling in the number since 2015. Even more striking, there are an additional 176 in the pipeline, so the breakneck growth in hyperscal... » read more

PCIe 5.0: A Key Interface Solution For The Evolving Data Center
By Vinitha Seevaratnam - 10 Sep, 2020 - Comments: 0

A great many developments are shaping the evolution of the data center. Enterprise workloads are increasingly shifting to the cloud, whether these be hosted or colocation implementations. The nature of workload traffic is changing such that data centers are architected to manage greater east-west (within the data center) communication. New workloads, with AI/ML (artificial intelligence/machine ... » read more

Scaling AI/ML Training Performance With HBM2E Memory
By Frank Ferro - 13 Aug, 2020 - Comments: 0

In my April SemiEngineering Low Power-High Performance blog, I wrote: “Today, AI/ML neural network training models can exceed 10 billion parameters, soon it will be over 100 billion.” “Soon” didn’t take long to arrive. At the end of May, OpenAI unveiled a new 175-billion parameter GPT-3 language model. This represented a more that 100X jump over the size of GPT-2’s 1.5 billion param... » read more

An Expanding Application Space For GDDR6 Memory
By Frank Ferro - 09 Jul, 2020 - Comments: 0

The origins of graphics double data rate (GDDR) memory can be traced to the rise of 3D gaming on PCs and consoles. The first GPUs used single data rate (SDR) and double data rate (DDR) DRAM, the same memory used for CPU main memory. The quest for higher frame rates at higher resolutions drove the need for a graphics-workload specific memory solution. The commercial success of gaming PCs and con... » read more

Data Center Scaling Requires New Interface Architectures
By Suresh Andani - 11 Jun, 2020 - Comments: 0

You can pick your favorite data points, but the bottom line is global data traffic is growing at an exponential rate driven by a confluence of megatrends. 5G networks are making possible billions of AI-powered IoT devices untethered from wired networks. Machine learning’s voracious appetite for enormous data sets is skyrocketing. Data intensive video streaming for both entertainment and busin... » read more

Enabling Chiplet And Co-Packaged Optics Architectures With 112G XSR SerDes
By Suresh Andani - 14 May, 2020 - Comments: 0

Conventional chip designs are struggling to achieve the scalability, as well as power, performance, and area (PPA), that are demanded of leading-edge designs. With the slowing of Moore’s Law, high complexity ASICs increasingly bump up against reticle limits. The demise of Dennard scaling means power consumption is a growing challenge. In this context, disaggregated architectures such as chipl... » read more

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