How AI In Edge Computing Drives 5G And The IoT


Edge computing, which is the concept of processing and analyzing data in servers closer to the applications they serve, is growing in popularity and opening new markets for established telecom providers, semiconductor startups, and new software ecosystems. It’s brilliant how technology has come together over the last several decades to enable this new space starting with Big Data and the idea... » read more

Dynamic CDC Jitter For Clock Domain Crossing (CDC) Signoff


By Himanshu Bhatt and Paras Mal Jain Detecting and debugging deep sequential CDC convergences using structural CDC verification is extremely difficult since doing a flat analysis on large designs has capacity related challenges, and even if verification tools can complete the analysis, it becomes a nightmare to debug the violations with complex sequential logic. Thus arises the need for dyna... » read more

Verifying Security In Processor-based SoCs


By Ruud Derwig and Nicole Fern Security in modern systems is of utmost importance. Device manufacturers are including multiple security features and attack protections into both the hardware and software design. For example, the Synopsys DesignWare ARC Processor IP includes many security functions in its SecureShield feature set. End-product system security, however, cannot be guaranteed by ... » read more

Implementing Low-Power Machine Learning In Smart IoT Applications


By Pieter van der Wolf and Dmitry Zakharov Increasingly, machine learning (ML) is being used to build devices with advanced functionalities. These devices apply machine learning technology that has been trained to recognize certain complex patterns from data captured by one or more sensors, such as voice commands captured by a microphone, and then performs an appropriate action. For example,... » read more

Shift Left Power-Aware Static Verification


Next-generation SoCs with advanced graphics, computing, machine learning (ML) and artificial intelligence (AI) capabilities are posing new unseen challenges in Low Power Verification. These techniques can introduce critical bugs into a design, especially when the power-management infrastructure interacts with signals that cross clock or reset domains. This can create additional clock-domain cro... » read more

High-Performance DSP And Control Processing For Complex 5G Requirements


In the early 2000s, digital signal processors (DSP) were simple in architecture and limited in performance, but complex in programming. However, they evolved to meet of the increased performance requirements of 3G cellular baseband modem applications. A typical 3G modem system would have a single DSP optimized for dual/quad SIMD MAC performance with basic DSP filter instructions like Fast Fouri... » read more

Is Your Functional Safety An Afterthought?


Imagine the air bag in your car not inflating during a collision or deploying without a crash during driving! These are two of the failure modes associated with the air bag in your car, none of which you as a driver have any control over. The severity of both these failures is of course very high, but which one would you rate as a higher hazard? The probability of getting into an accident is lo... » read more

Accurate Power Analysis Using Real Software Workloads


Over the last decade or so, power consumption has become a major issue in the design of many types of electronic products. Of course, power has always mattered for battery-operated devices, but the complexity of portable electronics and the size of the chips they contain have grown significantly. For plugged-in devices, from desktop computers to server racks in a data center, power plays a majo... » read more

Building Your First Chip For Artificial Intelligence? Read This First


As artificial intelligence (AI) capabilities enter new markets, the IP selected for integration provides the critical components of the AI SoC. But beyond the IP, designers are finding a clear advantage in leveraging AI expertise, services, and tools to ensure the design is delivered on time, with a high level of quality and value to the end customer for new and innovative applications. Over... » read more

The Rising Importance Of Design Planning


Design Planning is often overlooked in the chip design flow. The front-end designer carefully architects the design functionality to produce golden RTL. This is then poured into the synthesis engine to produce logic gates. The synthesized netlist is then thrown over the wall by the front-end designer for physical implementation. The back-end designer receives a gate-level netlist, timing con... » read more

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