Introducing Nanosheets Into Complementary-Field Effect Transistors (CFETs)


In our November 2019 blog [1], we discussed using virtual fabrication (SEMulator3D) to benchmark different process integration options for Complementary-FET (CFET) fabrication. CFET is a CMOS architecture that was proposed by imec in 2018 [2]. This architecture contains p- and n-MOSFET structures built on top of each other, instead of having them located side-by-side. In our previous blog, we r... » read more

The Chemistry Of Semiconductors


At each new process node, the chemistry of chip manufacturing has become much more complex than at previous nodes. But at 5nm and below, it's going to get orders of magnitude more complex. For the first few decades, the chemistry of chips was largely shielded from view for most of the industry. Caustic gases were relatively well understood because they are a potential health hazard, but the ... » read more

Best Practices In Business Continuity Planning


Cameron Burks, head of Global Security, Enterprise Business Resiliency and Health, Environment & Safety with Adobe Systems, and a member of the White House Task Force for COVID-19 response, briefed members of SEMI’s IT Leadership (ITL) and Environment, Health & Safety (EHS) groups on April 20, 2020, on enterprise resiliency principals specific to the current COVID-19 crisis. Burk... » read more

Fan-Out Wafer-Level Packaging And Copper Electrodeposition


By Steven T. Mayer, Bryan Buckalew, and Kari Thorkelsson As integrated circuit designers bring more sophisticated chip functionality into smaller spaces, heterogeneous integration, including 3D stacking of devices, becomes an increasingly useful and cost-effective way of mixing and connecting various functional technologies. One of the heterogeneous integration platforms gaining increased ac... » read more

Identifying And Preventing Process Failures At 7nm


Device yield is highly dependent upon proper process targeting and variation control of fabrication steps, particularly at advanced nodes with smaller feature sizes. Traditionally, cross-correlation and analysis of thousands of test data points have been required to identify and prevent process failures. This is very costly in terms of both time and money. Fortunately, semiconductor virtual fab... » read more

Scaling At The Angstrom Level


It now appears likely that 2nm will happen, and possibly the next node or two beyond that. What isn't clear is what those chips will be used for, by whom, and what they ultimately will look like. The uncertainty isn't about the technical challenges. The semiconductor industry understands the implications of every step of the manufacturing process down to the sub-nanometer level, including ho... » read more

Taking A Pulse On The IC Biz


It’s been a difficult period for the semiconductor industry. The coronavirus outbreak has put a damper on what was supposed to be a strong year in the semiconductor industry in 2020. Many are holding out hopes for a rebound in the second half of the year. That’s still a big unknown. The forecasts are gloomy. For example, VLSI Research has three different scenarios for the semiconduc... » read more

Gradual Rebound Or Slight Dip


Uncertainty has gripped the silicon wafer market as the COVID-19 pandemic threatens to upend growth projections for 2020. Declines in both shipments and revenue plagued the silicon wafer market in 2019, a downturn that had given way to optimism for 2020 with rising expectations for normalizing inventory levels, memory market improvements, data center market growth and the 5G market takeoff. ... » read more

Artificial Intelligence Is Everywhere


It’s pretty hard to talk about technology today without artificial intelligence, or AI, entering into the conversation. It seems to be everywhere… and growing. Businesses are using it to operate more efficiently, it’s resulting in safer and more useful products, and it has the promise of allowing us to personalize our worlds as devices learn our preferences. The age of AI AI refers to t... » read more

The Impact Of EUV Resist Thickness On Via Patterning Uniformity


Via patterning at advanced nodes requires extremely low critical dimension (CD) values, typically below 30nm. Controlling these dimensions is a serious challenge, since there are many inherent sources of variation during lithography and etch processing. Coventor personnel, in conjunction with our colleagues from ASML and imec, recently looked at the impact of Extreme Ultraviolet lithography (EU... » read more

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