Package Integrated Vapor Chamber Heat Spreaders


With continuous increases in computational demand in nearly all electronics market segments, even historically lower power packaging is being driven into challenging thermal management situations. Node shrink alone is reaching a limit in maintaining track with Moore’s law. The economics and yield challenges of large monolithic system on chip (SoC) designs are driving the development of silico... » read more

The High NA EUV Imperative: How Computational Lithography Solutions Enable Us To Think Smaller


The future of computing depends on miniaturization, and extreme ultraviolet lithography (EUV) is one key enabler. Until recently, we have relied on low numerical aperture (NA) EUV systems with an aperture of 0.33 to help us reduce the size of integrated circuits (ICs). As with deep ultraviolet (DUV) technology, this has begun to reach its limits. High NA EUV lithography with a 0.55 aperture rep... » read more

ESD Alliance And SEMI Efforts To Combat Design Automation Software Piracy


Piracy is a growing concern for all software providers, especially those of us with complex and specialized software, such as chip design automation software that is expensive to develop and maintain. That’s why the Electronic System Design Alliance (ESD Alliance), a SEMI Technology Community, spearheaded an industry joint development effort to develop a server certification protocol that ... » read more

Intel, And Others, Inside


Intel this week made a strong case for how it will regain global process technology leadership, unfurling an aggressive technology and business roadmap that includes everything from several more process node shrinks that ultimately could scale into the single-digit angstrom range to a broad shift in how it approaches the market. Both will be essential for processing the huge amount of data for ... » read more

Techniques To Identify And Correct Asymmetric Wafer Map Defects Caused By Design And Process Errors


Asymmetries in wafer map defects are usually treated as random production hardware defects. For example, asymmetric wafer defects can be caused by particles inadvertently deposited on a wafer during any number of process steps. In this article, I want to share a different mechanism that can cause wafer defects. Namely, that these defects can be structural defects that are caused by a biased dep... » read more

Utilizing Artificial Intelligence For Efficient Semiconductor Manufacturing


The challenges before semiconductor fabs are expansive and evolving. As the size of chips shrinks from nanometers to eventually angstroms, the complexity of the manufacturing process increases in response. It can take hundreds of process steps and more than a month to process a single wafer. It can subsequently take more than another month to go through the assembly, testing, and packaging st... » read more

Integrating Digital Twins In Semiconductor Operations


By Mark da Silva, Nishita Rao and Karim Somani Chipmakers must adopt transformative technologies including Digital Twins (DT) to keep pace with unprecedented global semiconductor industry growth that is expected to drive its total market value to $1 trillion[1] as soon as 2030. Leveraging predictive modeling and other efficiency-enhancing innovations, DTs promise to optimize semiconductor d... » read more

Using TCAD To Simulate Wide-Bandgap Materials For Electronics Design


Wide-bandgap (WBG) semiconductors are a class of materials that can offer a range of advantages over silicon. These materials can operate at higher voltages and higher temperatures, serving as critical enablers of innovation in Power and RF applications and functioning in a wider range of environments that are sometimes extreme. Electronics applications benefit from these wide-bandgap materials... » read more

Electromigration Performance Of Fine-Line Cu Redistribution Layer (RDL) For HDFO Packaging


The downsizing trend of devices gives rise to continuous demands of increasing input/output (I/O) and circuit density, and these needs encourage the development of a High-Density Fan-Out (HDFO) package with fine copper (Cu) redistribution layer (RDL). For mobile and networking application with high performance, HDFO is an emerging solution because aggressive design rules can be applied to HDFO ... » read more

Developing ReRAM As Next Generation On-Chip Memory For Machine Learning, Image Processing And Other Advanced CPU Applications


In modern CPU device operation, 80% to 90% of energy consumption and timing delays are caused by the movement of data between the CPU and off-chip memory. To alleviate this performance concern, designers are adding additional on-chip memory to their CPUs. Traditionally, SRAM has been the most widely used on-chip CPU memory type. Unfortunately, SRAM is currently limited to a size of hundreds of ... » read more

← Older posts