Materials, Magnetism & Quantum Physics


For the past half-century, chipmakers have been following the same roadmap for improving performance in chips and reducing the cost of chips. That has proven tremendously effective in reducing costs and packing computing into a smaller space, allowing people to carry around what used to be a multi-million-dollar mainframe in their pocket. That approach is beginning to lose momentum. It's ge... » read more

What’s Next In R&D?


Luc Van den hove, president and chief executive of Imec, sat down with Semiconductor Engineering to discuss R&D challenges and what’s next in the arena. The Belgium R&D organization is working on AI, DNA storage, EUV, semiconductors and other technologies. What follows are excerpts of that conversation. SE: Moore’s Law is slowing down. And it is becoming more expensive to move fr... » read more

Etch Techniques for Next-Generation Storage-Class Memory


Chipmakers make abundant use of two very different functional classes of memory in their products. For operational use (main/primary memory) where speed is critical, DRAM and SRAM are employed, whereas for long-term storage, flash memory – in particular NAND – provides the high capacity at low cost needed. For both classes, efforts to improve speed, capacity, and power usage are ongoing. To... » read more

What Else Is In A Node?


In part one of this blog, I reported on the 2018 Industry Strategy Symposium (ISS) where Dan Hutcheson of VLSI Research led a panel with representatives of Synopsys, NVIDIA, Intel, ASML and Applied Materials. The participants discussed how the industry is focused on simultaneously squeezing more capabilities from leading-nodes, inter-nodes and trailing-nodes to drive advances in computing. I to... » read more

System-In-Package Vs. eNVM


The booming automotive and IoT markets are driving increasing demand for microcontrollers (MCUs). Recent forecasts project that the overall MCU compound annual growth rate (CAGR) will reach 4% over the next five years, and in particular the automotive MCU CAGR could reach close to 14%. Non-volatile memory (NVM) is a critical element of MCUs, as it is needed not only to store the code, but al... » read more

Combining Human Intelligence And Smart Machines


By Nancy Greco, Dave Mayewski, James Moyne, Paul Werbaneth The spacecraft Discovery and its HAL 9000 computer system had a digital twin. Stanley Kubrick’s seminal film “2001: A Space Odyssey” had its theatrical release 50 years ago this April. “2001” isn’t just a great science fiction film. Rather, it’s a great work of cinema overall, across any category. (The American Film... » read more

Can AI Alter The Burgeoning Design Cost Trend?


Everyone in the semiconductor design arena has experienced or at least observed the impact of increasing costs for complex SoC silicon. Semico’s recently released report entitled "Silicon and Software Design Cost Analysis" reveals the cost associated with a first time design effort for a high-end, advanced performance multicore SoC using 7nm process technology can top $195M for both the silic... » read more

Delivering On The Promise Of Self-Driving Cars


Self-driving cars have been all the rage in both the trade and popular press in recent years. I prefer the term “autonomous vehicles,” which more broadly captures the possibilities, encompassing not only small passenger vehicles but mass transit and industrial vehicles as well. Depending on who’s talking, we will all be riding in fully autonomous vehicles in five to 25 years. The five-... » read more

What’s In A Node?


In an environment where process nodes are no longer consistently delivering the level of improvements predicted by Moore’s Law, the industry will continue to develop “inter-nodes” as a way to deliver incremental improvements in lieu of “full-nodes.” A shift in market requirements, in part due to the rise of AI and IoT, is increasing emphasis on trailing-nodes. When it comes to leading... » read more

Transistor-Level Performance Evaluation Based On Wafer-Level Process Modeling


Three years ago, I wrote a blog entitled “Linking Virtual Wafer Fabrication Modeling with Device-level TCAD Simulation,” in which I described the seamless connection between the SEMulator3D virtual wafer fabrication software platform and external third-party TCAD software. I’m now happy to report that device-level I-V performance analysis is now a built-in module within the SEMulator3D so... » read more

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