category: Blogs – MD

category: IoT, Security & Automotive

Examining Mechanical Deformation In Advanced Logic Devices To Enhance Yield
By Sandy Wen - 19 Jun, 2025 - Comments: 0

By Sandy Wen and Jacky Huang As dimensions shrink and aspect ratios increase in advanced logic devices, it is increasingly important to reduce structural device variation. Structural device variations can be a proxy for device yield. These variations might include critical dimension (CD), gate CD, gate height, and proximity between neighboring vias. One contributor to structural device v... » read more

How To Catch “Disappearing” Latent Defects
By Mike LaTorraca - 19 Jun, 2025 - Comments: 0

Automotive is demanding more emphasis on chip reliability. By 2020, electronic devices will account for over 35% of the manufacturing cost of an automobile, and by 2030, that number is expected to rise to 50%. Tens of thousands of cars are manufactured each day, with each car using thousands of chips — and if even one of those chips fails in the field it may have disastrous consequences: los... » read more

Variable Bias Completes The PLDC Model And Offers Superior MPC Results
By Aki Fujimura - 19 Jun, 2025 - Comments: 0

This is the third in a three-blog series on PLDC. The first installment was “Improving Uniformity and Linearity for All Masks,” from January 29, 2025. The second blog was “Three Ways Curvy ILT Together with PLDC Improves Wafer Uniformity,” from April 18, 2025. In 2024, the eBeam Initiative Luminaries Survey found that the number one concern in adoption of curvilinear mask features wa... » read more

Improving Fab Engineering Efficiency With Autonomous Data Analytics
By Peter Barar - 19 Jun, 2025 - Comments: 0

During my earlier career as a process integration engineer, one of my primary responsibilities was to find yield enhancement opportunities by investigating underlying relationships between bin failures and process parameters within the fab. While performing this analysis, there were many impediments to identifying relationships among different data types: sort maps, electrical test maps, parame... » read more

Path To Net-Zero Emissions In IC Packaging
By Louie Huang - 19 Jun, 2025 - Comments: 0

To strengthen climate resilience and accelerate towards net-zero emissions, ASE has implemented comprehensive carbon reduction strategies and management frameworks to practice responsible actions and achieve performance results. In our efforts to reduce our carbon footprint, we strive to design production facilities and processes that prioritize eco-efficient production and the creation of en... » read more

Critical Minerals Due Diligence And The Semiconductor Supply Chain
By Kimberly Harrison - 19 Jun, 2025 - Comments: 0

“Critical minerals our world needs for electric vehicles and semiconductors can be found here. Clean energy we need to power artificial intelligence data centers and economic growth can be built here.”[1] This statement was made by former US President Joseph Biden during his visit to Angola in December 2024 to support a US-funded railroad project called the Lobito Corridor. The railroad wou... » read more

Photomask Japan 2025: A Strong Signal For The Future Of Our Industry
By Leo Pang - 02 Jun, 2025 - Comments: 0

Photomask Japan (PMJ) 2025 was, without a doubt, the most exciting edition I’ve attended in recent years. From a surge in attendance to a packed agenda full of technical depth and forward-looking insights, this year’s event reflected the growing momentum and innovation across the photomask and eBeam ecosystem. Let’s start with the numbers—624 attendees. That’s a significant jump fr... » read more

Maximizing Signal Integrity: Fine-Tuning Via Impedance In HDFO Architectures
By Tsung Ting Lee - 22 May, 2025 - Comments: 0

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most of the electrical properties cannot be measured by instruments. Therefore, this study uses the indirect method to determine the impedance information of the via and match the impedance. Since the v... » read more

Revolutionizing Semiconductor Development With GPU-Enhanced Atomistic Modeling
By Anders Blom - 22 May, 2025 - Comments: 1

There are many challenges in the development of a modern semiconductor chip, from front-end architecture simulation to final signoff. Volume manufacturing has its own set of challenges, while silicon lifecycle management (SLM) extends into field deployment and aging concerns. Underlying this entire development flow, however, lie the materials used to build the actual chips. Guiding the explorat... » read more

Laser-Focused Results: Improving EUV Line Edge Roughness With Ion Beam Etching
By Timothy Yang - 22 May, 2025 - Comments: 1

Extreme ultraviolet (EUV) lithography exposed resist patterns can exhibit excessive line edge roughness (LER) and line width roughness (LWR) due to random or shot noise. Increasing the EUV exposure dose can reduce LER/LWR, but it also decreases wafer throughput, which is highly undesirable given the EUV tool’s high operating costs. Ion beam etching (IBE) can directionally etch away roug... » read more

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