A Hybrid PLP Technology Based On A 650mm x 650mm Platform


A panel-level (PL) approach to fan-out (FO) packaging has been discussed for several years to reduce the cost of chip-first FO packaging based on redistribution layer (RDL) technology. More recently, multilayer high-density chip-last packages have been introduced for more advanced applications. This technology would also benefit from PL processing for cost reduction. Due to the large package di... » read more

Improving Gate All Around Transistor Performance Using Virtual Process Window Exploration


As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF [1]. One method to overcome this problem is to move away from planar transistor architectures toward 3D devices. Gate-all-around (GAA) architectures are an example of this type of 3D device [2]. In a GAA transistor, the gate oxide surrounds the channel in all directions.... » read more

Multi-Beam Writers Are Driving EUV Mask Development


By Jan Hendrik Peters (bmbg consult) and Ines Stolberg (Vistec Electron Beam) The European Mask and Lithography Conference (EMLC) 2023, held in Dresden this past June, was attended by about 180 people and over 60 talks and posters were presented. With several keynote and invited talks over two and a half days, the conference gave an overview of the semiconductor and technology landscape in E... » read more

Smarter Systems Through Heterogeneous Integration: Highlights From 3D & Systems Summit


It has taken decades of research and development and strong commitment to various industry programs, but the stars are finally aligning for 3D semiconductor systems. No one could have left the 3D & Systems Summit 2023 – held in late June in Dresden – with any doubt that heterogeneous integration, enabled by increasingly mature 3D packaging technologies, is becoming a key driver of the s... » read more

High-Density Fan-Out Packaging With Fine Pitch Embedded Trace RDL


The needs of high-performance devices for artificial intelligence (AI), high performance computing (HPC) and data center applications have drastically accelerated during the Covid-19 pandemic period. At the same time, the integrated circuit (IC) industry struggles to minimize the silicon technology node to satisfy the endless requirements of computing performance within tight cost constraints. ... » read more

Improving DRAM Device Performance Through Saddle Fin Process Optimization


As DRAM technology nodes have scaled down, access transistor issues have been highlighted due to weak gate controllability. Saddle Fins with Buried Channel Array Transistors (BCAT) have subsequently been introduced to increase channel length, prevent short channel effects, and increase data retention times [1]. However, at technology nodes beyond 20nm, securing sufficient device performance (su... » read more

A Technical Guide To Selecting A Photosensitive Permanent Bonding Material


A photosensitive permanent bonding material enables the creation of high-quality permanent bonds between dissimilar materials used in the creation of MEMS and sensors. Having a thorough understanding of the materials and product performance is crucial to the success of the end application. In this article, we explore nine criteria used to evaluate a polymeric photosensitive permanent bonding ma... » read more

A New Class Of Actuators Mimicking Human Muscle


Developing robots with human-like muscles that produce autonomous movement is not possible using traditional rigid, high-voltage electronics. However, recent research funded by FlexTech, a SEMI Technology community, shows promise in incorporating microcircuits to do just that by directly controlling and operating HASEL actuators. The innovation could guide intelligent, goal-oriented robots in ... » read more

Next Gen Laser Assisted Bonding (LAB) Technology


In the semiconductor market, there are many applications including smartphone, tablets, central processing units (CPUs), artificial intelligence (AI), data cloud and more that are expecting rapid growth. Among them, CPU data processing, AI and data cloud require much higher power consumption than smart phones or tablets. For the higher power applications, Flip Chip ball grid array (FCBGA) or 2.... » read more

The Impact Of Metal Gate Recess Profile On Transistor Resistance And Capacitance


In logic devices such as finFETs (field-effect transistors), metal gate parasitic capacitance can negatively impact electrical performance. One way to reduce this parasitic capacitance is to optimize the metal gate recess dimensions. However, there are limits to reducing this capacitance if you simply remove more of the metal material, since this can modify capacitance unexpectedly through chan... » read more

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