category: Blogs – MD

category: IoT, Security & Automotive

Semiconductor Photomask Market Poised For Another Year Of Growth
By Jan Willis - 19 Sep, 2024 - Comments: 0

The semiconductor photomask market, a crucial component in chip manufacturing, is on track for another year of robust growth. This growth trajectory is supported by a series of technological advancements and market trends that continue to drive innovation in the industry. As the annual SPIE Photomask Technology Conference approaches in early October in Monterey, California, it presents an oppor... » read more

Smart Manufacturing, Smart Data-AI, And Future Of Computing
By Melissa Grupen-Shemansky - 19 Sep, 2024 - Comments: 0

By Melissa Grupen-Shemansky, Pushkar Apte, and Mark da Silva Use of machine learning and artificial intelligence (ML/AI) is on an exponential rise across fields1 including all aspects of the semiconductor industry. In the last decade, the use of ML/AI exploded in the areas of speech recognition, facial recognition, smart phone features, search engines and now large language models like Chat... » read more

Current Characterization Of Various Cu RDL Designs In Wafer Level Packages (WLP)
By JeongMin Ju - 15 Aug, 2024 - Comments: 0

Copper (Cu) redistribution layer (RDL) technology is used to interconnect chips in various high current Wafer Level Packaging (WLP) applications. Typically, Cu RDLs with thicknesses of 5-9 µm and widths of 5-20 µm are used for high current sourcing. In this case, the temperature of the Cu RDL metal line increases due to the Joule heat generated when current passes through the metal line. If a... » read more

Bringing Curvilinear Data To Mask Data Prep
By Al Blais - 15 Aug, 2024 - Comments: 0

Advanced nodes that have been leveraging curvilinear correction with technologies such as ILT and curvilinear OPC are increasingly requiring the use of curvilinear masks to meet advanced feature size and pitch requirements. However, building curvilinear masks with standard OASIS file formats can come at the cost of large file sizes, increased turnaround time, and reduced quality of results. The... » read more

Improving Parasitic Capacitance In Next-Generation DRAM Devices
By Dempsey Deng - 15 Aug, 2024 - Comments: 0

As conventional DRAM devices continue to shrink, increases in parasitic capacitance at smaller dimensions can negatively impact device performance. New DRAM structures may be needed in the future, to lower total capacitance and achieve acceptable device performance. In this study, we compare the parasitic capacitance of a 6F2 honeycomb dynamic random-access memory (DRAM) device to the parasitic... » read more

Five Questions To Ask When Selecting A Temporary Bonding And Debonding System
By Jessica Albright - 15 Aug, 2024 - Comments: 0

High-bandwidth memory blocks (HBM), microprocessors, field-programmable gate arrays (FPGA), AI accelerators, and other devices used in advanced system-level packaging all rely on temporary bonding and debonding systems to shrink their footprint. Understanding which properties play the most crucial role in device reliability and efficient production will ensure you are maximizing your yield, whi... » read more

Securing Supply Chains At SEMICON West 2024
By John Cooney - 15 Aug, 2024 - Comments: 0

Jose Fernandez, U.S. Under Secretary of State for Economic Growth, Energy, and the Environment, sat down with Joe Stockunas, President of SEMI Americas, for a fireside chat on the CEO Summit keynote stage at SEMICON West 2024. In the Securing Critical Supply Chains for the 21st Century discussion, Fernandez emphasized the need to form partnerships to address vulnerabilities as the key to cre... » read more

Improving Line Edge Roughness Using Virtual Fabrication
By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging
By Heejun Jang - 23 Jul, 2024 - Comments: 0

With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes
By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

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