Selective Removal For Stronger Fins


By Matt Cogorno and Toshihiko Miyashita Remember when we could charge our mobile phones on a Sunday and not even think about it again until the next weekend? There was a time when battery life wasn’t even in the top ten concerns when purchasing a mobile phone. Today however, smartphones are constantly being used for computing, gaming, video streaming and other power-hungry applications, so... » read more

More Devices Will See In 3D


The 3D optical sensing market is once again surging – and it’s all thanks to Apple. What will we see in the next wave of end products enhanced by this technology, how will other market segments approach – and eventually use – 3D optical sensing, and which suppliers stand to gain the most from this very vital technology? Although 3D sensing, facial recognition and optical authenticati... » read more

Slow And Cautious Start To 2019 For Memory Manufacturers


Both NAND and DRAM prices began dropping in the second half of 2018 after a couple years at record highs. Product oversupply and excess inventories are signaling a bleak outlook for the memory market in the first half of 2019. With these conditions in mind, SK Hynix and Samsung have slowed or put on hold their plans for capacity expansion in 2H18 and 2019. The chart below shows DRAM capacity... » read more

5 Top Storylines For NAND Biz


2019 is expected to be a busy, if not difficult, year in the NAND flash memory market. Vendors will continue to ramp up 3D NAND, the successor to traditional 2D or planar NAND. Then, over the last year, prices for NAND have dropped with oversupply in the market. What’s in store in 2019? Vendors are expected to rush out their next-generation products. Then, there is a debate whether the... » read more

Creating Higher Density 3D NAND Structures


3D NAND flash memory has enabled a new generation of non-volatile solid-state storage useful in nearly every electronic device imaginable. 3D NAND can achieve data densities exceeding those of 2D NAND structures, even when fabricated on later generation technology nodes. The methods used to increase storage capacity come with potentially significant tradeoffs in memory storage, structural sta... » read more

Multiple Approaches To Memory Challenges


As we enter the era of Big Data and Artificial Intelligence (AI), it is amazing to think about the possibilities for a truly seismic shift in the changing requirements for memory solutions. The massive amount of data humans generate every year is astounding and yet is expected to increase five-fold in the next few years from machine-generated data. Further compounding this growth is the emergin... » read more

New Model To Advance Industry Roadmaps


Economically, geopolitically and technologically – with visibility for the future unclear – there couldn’t be a better time for the microelectronics industry to take stock of its options. The U.S. government obsesses with whether to build a bigger wall. The trade war continues to have significant impact across the globe, straining U.S./China relationships to the point of saber rattling... » read more

Fearless chip and fab tool forecasts


2019 is expected to be a challenging, if not confusing, year for the semiconductor and fab equipment industries. For example, Apple recently issued a warning about lackluster smartphone demand, which impacted several IC vendors and foundries. Then, the memory market is plummeting. In addition, the 10nm/7nm transition has proven to be difficult for many. And let’s not forget the geopolitica... » read more

Analyzing Worst-Case Silicon Photonic Device Performance Through Process Modeling And Optical Simulation


Silicon photonics is an emerging and rapidly-expanding design platform that promises to enable higher-bandwidth communication and other applications. One of the best qualities of silicon photonics is its ability to leverage existing CMOS fabrication equipment and process flows. However, this means that it is subject to the same process defects and variations. Previous blog posts [References 1,2... » read more

Keeping Up Power And Performance With Cobalt


Chip designers require simultaneous improvements in “PPAC”: power, performance and area/cost (Fig. 1). Achieving these improvements is becoming increasingly difficult as classic Moore's Law scaling slows. What's needed is a new playbook for the industry consisting of new materials, new architectures, new 3D structures within the chip, new methods to shrink feature geometries, and advanced p... » read more

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