Over 65% Smartphone RF Switches SOI, Says Yole; Power Amps Next


By Adele Hars The industry research firm Yole Développement says that more than 65 percent of substrates used in fabricating switches for handsets are SOI-based. This is a high-growth part of the market, putting up double-digit increases. Like a standard SOI wafer, an RF SOI substrate has an active (“top”) layer on which CMOS transistors are built, with an isolating (“BOx”) ... » read more

Interacting With Printed Sensors


By Michael P.C. Watts If there is one feature that distinguishes all our modern portable devices from the traditional PC (a wonderful concept—the “traditional PC”), it’s the way we interact. Separate keyboards are done. It's all touchscreens on pretty much everything, along with other sensor opportunities. There are many uses for the built-in cameras in cell phones from videoconfere... » read more

Materials, Software And Techniques


The future of advanced semiconductor technology is about to split evenly into three different areas. On the leading edge of manufacturing, Applied Materials CEO Mike Splinter called it correctly—it’s all about materials. Just shrinking features isn’t buying much anymore. In fact, at advanced nodes, with extra margin built into designs, it frequently doesn’t buy anything except extra ... » read more

The Alphabet Soup Of New Material Science


By Joanne Itow Escaping the scorching Arizona temperatures is only one reason why I always look forward to Semicon West. This year’s event was packed with an exceptional variety of activities and vendors. What was the most memorable take-away from the show? There were plenty of panels, presentation and networking discussions on the 450mm wafer transition and EUV. But the biggest thing that I... » read more

Changes And Challenges


At 130nm, the shift to copper interconnects and 300mm wafer sizes was considered to be the most difficult transition in its long and incredibly efficient history. The next chapter will be even tougher. It’s not that change is a foreign concept to semiconductor design and manufacturing. In fact, it’s probably the only constant over the past 50 years. But in the past, those changes tended ... » read more

The New Hybrid World: Vision And Reality


SAN FRANCISCO—You know the famous scene from the movie “The Graduate,” in which a young Dustin Hoffman is offered investment advice by a businessman. “I want to say just one word to you…just one word. Are you listening? Plastics.” Today, Hoffman’s character Benjamin Braddock might hear two words: “Integrated objects.” At least that’s how Ross Bringans from PARC sees... » read more

You Can’t Get There From Here


By David Abercrombie In my last article, I reviewed the aspects of cell design that are affected by double patterning (DP). This time, I’ll discuss how automatic routing is affected by DP. Let’s begin by looking at the interaction between decisions made at the cell design level and decisions made at the routing level. One key routing decision is whether or not you will allow cell-to-cel... » read more

Mobility Gets A Boost With Expanded Epi Applications


By Jeremy Zelenko Even as industry moves into the era of the high k metal gate (HKMG) and FinFET transistor, chipmakers continue to seek ways to improve device performance. One of the latest advances and the subject of an Applied Materials announcement made today is to extend epitaxial deposition from PMOS to NMOS transistors. Implementing an NMOS epitaxy (epi) process in addition to the estab... » read more

GloFo Says 28nm FD-SOI Die Cost Much Less Than 28nm Bulk HPP


Posted by Adele Hars, Editor-in-Chief, Advanced Substrate News ~  ~ According to Shigeru Shimauchi, Country Manager, GlobalFoundries Japan, for the same level of performance, the die cost for 28nm FD-SOI will be substantially less than for 28nm bulk HPP (“high performance-plus”). Specifically, to get a 30%  increase in performance over 28nm bulk LPS PolySiON, HPP increases die ... » read more

Let’s All Meet At The Via Bar!


By Jean-Marie Brunet At 28 nm and below, a variety of new design requirements are forcing us to adjust the traditional layout and verification process of digital designs. The use of vias, in particular, has been significantly impacted. New via types have been introduced, and the addition of double patterning, FinFETS, and other new design techniques has not only generated a considerable increa... » read more

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