category: Blogs – PTES

category: IoT, Security & Automotive

Nip The Defect In The Bud
By Melvin Lee - 12 Apr, 2022 - Comments: 0

As technology nodes shrink, end users are designing systems where each chip element is being targeted for a specific technology and manufacturing node. While designing chip functionality to address specific technology nodes optimizes a chip’s performance regarding that functionality, this performance comes at a cost: additional chips will need to be designed, developed, processed, and assembl... » read more

Automate Memory Test Through A Shared Bus Interface
By Harshitha Kodali - 12 Apr, 2022 - Comments: 0

The use of memory-heavy IP in SoCs for automotive, artificial intelligence (AI), and processor applications is steadily increasing. However, these memory-heavy IP often have only a single access point for testing the memories. A shared bus architecture allows testing and repairing memories within IP cores through a single access point referred to as a shared bus interface. Within this interface... » read more

Detecting Spatial Blotches In Image Sensor Devices
By Christos Pantelidis - 12 Apr, 2022 - Comments: 0

One of the most common defects in image sensor devices is spatial blotches. The appearance of blotches in image sensors is a regular occurrence and may be generated by internal moving parts or may be moved by air currents within the camera. Composed of two main statistical methods, the first module employs an inferential method, applying a spatial segmentation of the current frame to obtain ... » read more

Site-To-Site Variation In Parallel Test
By Ed Seng - 16 Mar, 2022 - Comments: 0

From wafer to system level test, parallel test execution delivers significant benefits, including reduced costs, yet it’s never as simple as that PowerPoint slide you present to management. An engineering effort is required to balance the thermo-electrical challenges that occur as you increase the number of sites to be tested, or the number of slots in a burn-in oven or system level te... » read more

Addressing The ABF Substrate Shortage With In-Line Monitoring
By Wesley Chou - 08 Mar, 2022 - Comments: 1

Ajinomoto build-up film (ABF) substrate has been a key component in chip manufacturing since its introduction shortly before the turn of the millennium. Substrates made with Ajinomoto build-up film – an electrical insulator designed for complex circuits – are found in PCs, routers, base stations, and servers. Looking ahead, the ABF substrate market will continue to grow, with revenue up ... » read more

A Practical Approach To DFT For Large SoCs And AI Architectures, Part II
By Rahul Singhal - 08 Mar, 2022 - Comments: 0

By Rahul Singhal and Giri Podichetty Part I of this article discusses the design-for-test (DFT) challenges of AI designs and strategies to address them at the die level. This part focuses on the test requirements of AI chips that integrate multiple dies and memories on the same package. Why 2.5D/3D chiplet-based designs for AI SoCs? Many semiconductor companies are adopting chiplet-based d... » read more

Enabling Silicon Lifecycle Solutions
By Aileen Ryan - 08 Mar, 2022 - Comments: 0

The concepts of product lifecycle management (PLM) should be familiar, although the semiconductor industry has yet to adopt a system for managing the entire lifecycle of a product from inception through design, realization, deployment, and field service, right through to end-of-life activities such as final disposal. Now, a combination of business and technical pressures is bringing PLM capabil... » read more

Assuring Reliable Processor Performance At Scale
By Uzi Baruch - 08 Mar, 2022 - Comments: 0

In today’s data center environment, resilience is key. Cloud providers are built on as-a-service business models, where uptime is critical to ensure their customers’ business continuity. Reputation and competitiveness require service at extremely high performance, low power, and increasing functionality, with zero tolerance for unplanned downtime or errors. If you’re a hyperscaler, o... » read more

Critical Moves: Advanced Logic Devices And CIS Benefit From Applications Using IRCD Metrology
By Nick Keller - 08 Feb, 2022 - Comments: 1

As 3D NAND continues to scale vertically — all in the name of increasing capacity and speed and reducing inefficiency and cost — maintaining channel hole critical dimension (CD) and shape uniformity becomes even more challenging. Faced with rising high-aspect ratios, addressing these challenges requires new inline non-destructive metrology to provide real-time process control. Infrared crit... » read more

Simplify DFT For Advanced SoCs
By Ron Press - 08 Feb, 2022 - Comments: 0

The purpose of electronic design automation (EDA) software is to solve SoC design problems and simplify the entire process. For design for test (DFT), this means aiming to streamline the DFT development for today’s large and complex designs. The technologies and methods developed through partnerships between EDA suppliers, foundries, and semiconductor companies should effectively reduce risk,... » read more

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