Test Gets Ready For Wi-Fi 7


New test solutions are emerging to address the test challenges associated with the forthcoming Wi-Fi 7 standard. Wi-Fi 7 covers the (so far, for Wi-Fi) unused frequency range between 6 GHz and 7.125 GHz, using up to 4096-QAM modulation schemes and up to 320MHz channel bandwidth (see figure 1). Fig. 1: Wi-Fi band ranges are shown here, including the 3x increase in bandwidth enabled by a... » read more

Engineering Test Station Facilitates Post-Silicon Validation


The semiconductor market is evolving, with devices becoming more complex as chip designers add cores and pursue 2.5D and 3D integration strategies. This complexity presents challenges extending from design and simulation through system-level test (SLT), where a device is exercised in mission mode, booting up an operating system and running end-user code, for example. These challenges arise f... » read more

Industrial Solutions For Machine-Learning-Enabled Yield Optimization And Test


This article summarizes the content of a paper developed and presented by Advantest at ETS 2022. By Sonny Banwari and Matthias Sauer According to market research firm Gartner, Inc., in assessing the completion rate of data science projects, as well as the bottom-line value they generate for their companies, only between 15 and 20 percent of these projects are ever completed. Moreover, of ... » read more

A Customized Low-Cost Approach For S-Parameter Validation Of ATE Test Fixtures


This article summarizes the content of a paper jointly developed and presented by Advantest and Infineon at TestConX 2022. Device under test (DUT) fixtures for ATE systems pose several verification challenges. Users need to measure the DUT test fixture quickly and easily, while making sure the measurements mimic the ATE-to-test-fixture interface performance and determining how to handle DUT ... » read more

Trends In Testing: New Challenges Create New Opportunities


As advancements in semiconductors and microelectronics soldier ahead into emerging, even uncharted, territory, new test challenges arise. To that end, let’s look at a few key trends and challenges that are driving opportunities for innovation in the test sector. Technology convergence has been a buzzword for some time, and this trend is only going to intensify with the heightened need to m... » read more

Harnessing The Power Of Data In Semiconductor Test


Every day, new methods are being developed to harvest, cleanse, integrate, and analyze data sources and extract from them useful, actionable intelligence to aid decision-making and other processes. This is true for a variety of industries, including semiconductor design, manufacturing, and test. Moore’s Law (figure 1) may be slowing with respect to traditional scaling of transistor critica... » read more

HSIO Loopback Turns Challenges Into Opportunities For Test At 112 Gbps


By Dave Armstrong and Don Thompson For both PCIe and Ethernet (IEEE 802.3,) signals are getting mighty small. With PCIe 5 reaching 32 Gbps (NRZ at 32 GBaud) and 802.3 reaching 112 Gbps (PAM4 at 56 GBaud), typical eye-mask limits are shrinking. Consequently, test requirements for high-speed I/O (HSIO) test are becoming daunting. HSIO test involves measurement of Tx eye height and width, co... » read more

Automotive Keyless Entry SoC Test Methodologies And Techniques


By Philip Brock, Louis Benton, Jr., and Jonvyn Wongso Passive Entry Passive Start (PEPS) technology has become standard in the automotive market for keyless operation. A secure wireless communication system, PEPS enables you to lock and unlock the vehicle, and start and stop the vehicle without physically using the key. Electronic functionality embedded in the key fob to interact with the ve... » read more

SLT Enables Test Content To Shift Right


By Dave Armstrong, Davette Berry, and Craig Snyder Increasing device complexity and the continuing drive for higher levels of quality are fostering a reconsideration of test strategies. To be effective, test engineers must choose how to optimally deploy test content, from wafer probing to system-level test (SLT). A March 2019 TestConX presentation1 outlines how test content is typically allo... » read more

Driving Toward Predictive Analytics With Dynamic Parametric Test


The foundation of parametric test within semiconductor manufacturing is its usefulness in determining that wafers have been fabricated properly. Foundries use parametric test results to help verify that wafers can be delivered to a customer. For IDMs, the test determines whether the wafers can be sent on for sorting. Usually inserted into the semiconductor manufacturing flow during wafer fabric... » read more

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