Squeezing Out More Test Compression


The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which t... » read more

A Breakthrough In Silicon Bring-Up


The current semiconductor market is seeing increasingly complex silicon devices for applications like 5G wireless communications, autonomous driving, and artificial intelligence. One of the ways designers are working to control design time and cost is through the adoption of IJTAG (IEEE 1687) for a plug-and-play style IP integration during design. The benefits of using IJTAG are still emerging,... » read more

The Single Best DFT Move You Can Make


A proven method to simplify a complex problem is to break it into smaller chunks. In the case of today’s large, complex SoCs, this means using hierarchical methods to design the blocks, then combine the results at the top level. While this sounds obvious, it hasn’t always been practical or technologically feasible to perform some tasks, like DFT, at the block level and translate that work s... » read more

Highly Efficient Scan Diagnosis With Dynamic Partitioning


Charged with the task of improving yield, product engineers need to find the location of defects in manufactured ICs quickly and efficiently. Typically, they use volume scan diagnosis to generate large amounts of data from failing test cycles, which is then analyzed to reveal the location of defects. Scan failure data provides the basis for many decisions in the failure analysis and yield impro... » read more

Hierarchical DFT On A Flat Layout Design


The use of hierarchical DFT methods is growing as design size and complexity stresses memory requirements and design schedules.  Hierarchical DFT divides the design into smaller pieces, creates test structures and patterns at the core level, then retargets the core patterns to the chip level. But, if you need to perform the physical place and route on the full flat design, can you still take a... » read more

Challenges Of Logic BiST In Automotive ICs


The electronics in passenger cars continues to grow, and much of it is bound by the strict functional safety requirements formalized in the ISO 26262 standard. The ICs that drive the electronics systems in automobiles are also increasingly complex, designed to execute artificial intelligence algorithms that govern emerging self-driving capabilities. Designers are quickly adopting comprehensi... » read more

Smart Plug-And-Play DFT For Arm Cores


Modern SoCs are experiencing continued growth in capabilities and design sizes with more and more subsystem IPs being implemented. These large, complex, multi-core SoCs need strategies for DFT and ATPG that effectively reduce DFT effort, minimize ATPG runtime, and still achieve the target test coverage. Hierarchical DFT enables designing and testing of these designs in a systematic and repeatab... » read more

Breakthrough For Scan Diagnosis With Machine Learning


Cell-aware diagnosis is a new and effective way to detect defects inside standard cells. Industry standard failure analysis (FA) results from a major foundry show that cell-aware diagnosis is very effective at increasing the resolution of the diagnosis by reducing the number of suspects in cell-internal defect data. With advanced technology nodes, we have more complex layout structures and f... » read more

How To Manage DFT For AI Chips


Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and Mythic are ASICs based on the novel, massively parallel architectures that maximize data processing capabilities for AI workloads. Others, like Intel, Nvidia, and AMD, are optimizing existing archite... » read more