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Planning Ahead For In-System Test Of Automotive ICs

The safe operation of automotive systems depends on robust real-time testing.

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Automobiles are increasingly more like electronic devices than mechanical platforms. As a share of the total cost of a car, electronics components have grown from about 5% in 1970 to 35% in 2010. Electronics are projected to account for 50% by 2030 (Deloitte, 2019). Some of the electronics are for passive operations, like display or In-Vehicle Infotainment (IVI) systems, but a growing proportion of the electronics and ASICs in automobiles run the safety-critical systems. These systems are held to very high standards of reliability and safety. Part of meeting those standards, including ISO 26262, is implementing robust in-system test to find errors that can affect the safe operation of the car. In-system test includes power-on self-test, power-off test, and self-test during functional operation.

Managing the requirements for testing automotive ICs takes more than just robust in-system test; it also calls for very high defect coverage during manufacturing test. Along with the growing design sizes and adoption of advanced manufacturing processes, ending up with a safety-compliant IC on time and on budget requires advanced planning and a scalable design-for-test (DFT) strategy.

Embedded deterministic test (EDT) has been the workhorse of DFT, delivering enough compression to contain the test costs during the era of Moore’s law. Today’s EDT solutions can achieve the very high defect coverage required for automotive ICs. After the IC becomes part of the automobile’s systems, it needs regular periodic testing during functional operation to ensure reliability, which is done through logic built-in-self test (LBIST). The DFT solution needs to handle this task too. Figure 1 illustrates the combined logic architecture of hybrid TK/LBIST.


Figure 1. The architecture of hybrid ATPG/LBIST logic used in Mentor’s Tessent TestKompress TK/LBIST hybrid DFT IP.

For automotive ICs that make use of EDT and also LBIST, you can combine the two technologies into a hybrid ATPG/LBIST method. The once-separate ATPG and LBIST logic have merged so the scan compression IP can also apply BIST tests, a technique that has gained increased adoption among automotive IC designers. The hybrid test method is made all the better with the addition of hybrid test points. Rather than using separate LBIST test points to address random pattern resistance and ATPG test points to reduce pattern count, you can use hybrid test points that target both scan compression and BIST to cut test time and cost significantly with no loss of test coverage.

Hybrid ATPG/LBIST and Hybrid Test Points
A hybrid ATPG/LBIST test strategy increases manufacturing test coverage and improves in-system test for mission-critical automotive ICs. The fully on-chip LBIST applies pseudo-random patterns to the circuit and responses are collected in a Multi-Input Signature Register (MISR). However, it may take a large number of patterns, and a relatively long amount of time, to reach the required coverage goals. Traditional LBIST test points (Figure 2) improve test coverage by breaking up areas within the circuit that are random-pattern resistant, such as large blocks of logic focused on encoding or decoding. Replacing the traditional LBIST test points with hybrid test points improves coverage even more. Looked at another way, hybrid test points use 10x fewer patterns to achieve the standard 90% coverage rate. The smaller test set helps the in-system test run faster, which is important for testing during functional operation.


Figure 2. BIST test points improve test coverage but can increase the number of patterns needed and increase the in-system test time.

Table 1 shows the improvement in test coverage with hybrid test points over EDT or LBIST test points separately. The average test coverage improvement between traditional LBIST test points and hybrid test points is 3.25%.


Table 1. Improvement in LBIST test coverage (TC) with three different test points. Mentor’s VersaPoint Hybrid ATPG/LBIST test points outperform either EDT or LBIST test points for test coverage.

Better together
Hybrid ATPG/LBIST test points combine all the benefits of EDT and LBIST test points and work better than either type of test point separately. They can target both compressed pattern count reduction and BIST coverage with more advanced test point analysis and insertion algorithms. For an automotive IC, hybrid test points deliver better in-system test coverage, which is important for meeting ISO 26262 requirements and achieving Automotive Safety Integrity Level (ASIL) C and D certification levels.

Several large semiconductor companies already use hybrid test points in their safety-critical DFT instead of separate LBIST and ATPG test points. It takes just a bit of extra planning to switch to a hybrid ATPG/LBIST test method, but the savings in test cost and getting a safety-compliant device to market faster is worth the effort.

Learn more in our whitepaper, Improving In-system test with Tessent VersaPoint test point technology.



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