Automotive Chip Design Workflow


Stewart Williams, senior technical marketing manager at Synopsys, talks about the consolidation of chips in a vehicle and the impact of 7/5nm on automotive SoC design, how to trade off power, performance, area and reliability, and how ISO 26262 impacts those variables. » read more

Ensuring Functional Safety In Design


Mohammed Abdelwahid (Ali), automotive logic test product manager at Mentor, a Siemens Business, discusses how to maximize coverage in the different ASIL standards for logic BiST, how to make testing more efficient, and what impact that has on area and test time. » read more

Planning Ahead For In-System Test Of Automotive ICs


Automobiles are increasingly more like electronic devices than mechanical platforms. As a share of the total cost of a car, electronics components have grown from about 5% in 1970 to 35% in 2010. Electronics are projected to account for 50% by 2030 (Deloitte, 2019). Some of the electronics are for passive operations, like display or In-Vehicle Infotainment (IVI) systems, but a growing proportio... » read more

Squeezing Out More Test Compression


The trend in semiconductors leads to more IC test data volume, longer test times, and higher test costs. Embedded deterministic test (EDT) has continued to deliver more compression, which has been quite effective at containing test costs. For many designs, standard test compressions is enough, but ICs for use in automotive and medical devices require a higher manufacturing test quality, which t... » read more

Challenges Of Logic BiST In Automotive ICs


The electronics in passenger cars continues to grow, and much of it is bound by the strict functional safety requirements formalized in the ISO 26262 standard. The ICs that drive the electronics systems in automobiles are also increasingly complex, designed to execute artificial intelligence algorithms that govern emerging self-driving capabilities. Designers are quickly adopting comprehensi... » read more

Improving Simulation Throughput Using The Xcelium Parallel Logic Simulator


Simulators have been around for a long time. First, there were interpreters in the ‘80s and ‘90s, and despite being relatively slow, they were a big step up from fabricating the design and hoping it worked. However, as designs continued to increase in size, the interpreters could not keep up with simulation needs, and innovation was required for simulators to keep pace with new technology. ... » read more

BiST Grows Up In Automotive


Test concepts and methods that have been used for many years in traditional semiconductor and SoC design are now being leveraged for automotive chips, but they need to be adapted and upgraded to enable monitoring of advanced automotive systems during operation of a vehicle. Automotive and safety critical designs have very high quality, reliability, and safety requirements, which pairs pe... » read more

Automotive Functional Safety Using LBIST and Other Detection Methods


Functional safety requirements for safety-critical applications are addressed with the insertion of safety mechanisms to detect and/or correct potential failures: their effectiveness is measured by diagnostic coverage (DC). Built-in-self-test, or BIST, originally developed for manufacturing test, can be used as a detection mechanism for functional safety. However, it requires original values to... » read more

IC Test: Doing It At The Right Place At The Right Time


In the real world, we are slaves to our environment. The decisions we make are dependent on the resources available at any given time. In school, I remember coming up with a binary decision diagram (BDD) variable-ordering algorithm that relied on partial BDDs. Was that the best algorithm to determine the variable ordering of a BDD for a design? Probably not. However, it was easy to do as a coll... » read more

Unified Compression and LBIST in a Physically Aware Environment


Unified compression is a new approach that unifies scan compression and logic built-in self-test (LBIST). It leverages recent innovations from Cadence in physically-aware design for test (DFT) to solve routing congestion and area issues from traditional discrete approaches and delivers a confident path to high-quality test. On a sample design, area savings of 35–47%, and scan wirelength savin... » read more

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