Don’t Let X Be A Problem For Logic BIST

Why unknowns create problems for test time and coverage.


By Rahul Singhal and Giri Podichetty

A failure in the operation of integrated circuits (ICs) or chips deployed in safety-critical applications such as automotive, medical, and aerospace could have catastrophic consequences. These failures could stem from defects in the chip that escaped manufacturing tests or from transient faults that can occur during system operation due to factors such as the operating environment. To avoid such failures, these ICs require the highest quality of manufacturing tests that achieve less than one defective-part-per-million (DPPM) and in-system test capabilities that ensure the safe functionality of the chips during system operation as defined by ISO 26262 standard. IC designers typically generate scan test patterns based on advanced fault models such as cell-aware, path-delay, transition, etc. to meet aggressive test quality goals and add design-for-test (DFT) such as logic BIST for in-system test.

Logic BIST is a key DFT component of the in-system test for testing the non-memory portion of the design. Unlike scan test where patterns are applied using an automatic-test-equipment (ATE) with scan test pins, the logic-BIST test patterns are generated on chip using a pseudo-random-pattern-generator (PRPG) and the test pattern responses are accumulated into a signature using a multiple-input-shift-register (MISR). The MISR signature is compared with the expected signature on or off chip to determine test pass/fail status. In addition to requiring high test-coverage, in-system test for ICs in safety-critical applications must have a short test time because the test is performed during the functional operation of the chip. One of the major factors impacting test time and test coverage with logic BIST is the paths in the design generating unknown (i.e. X) simulation values because an X corrupts the MISR signature accumulated over several test patterns or test intervals. This results in test coverage loss or requires more test patterns to achieve the target test coverage which increases test time. Standard logic BIST solutions need an X-clean design to avoid this problem.

Xs occur at different stages of the design development cycle due to a variety of reasons, including unmodeled circuit behavior, missing design initializations, and unaccounted timing paths in static timing analysis (STA). With standard logic BIST, designers follow an approach of eliminating Xs either by design changes or handling them by masking the scan chains during pattern generation at the cost of design schedule or test quality. To eliminate Xs before the place-and-route process, the designers typically opt for design change instead of masking scan chains because the turn-around time for a design change is short at this stage (as shown in figure 1). It is, however, common for new Xs to appear with the addition of timing information after the place-and-route process. This scenario is shown in figure 2, where designers are forced to make a tradeoff between significant delays due to design change/re-spin and lower test quality due to chain masking. The unknown logic values pose an even tougher challenge post-silicon. With today’s aggressive design practices and technology nodes, it is nearly impossible to predict the unknown values that would occur post-silicon due to factors such as sophisticated fault models, timing marginalities and operating parameter variation. As depicted in figure 3, a design change isn’t possible in silicon and the only option would be to compromise on test-coverage and test-time by masking the chains. Due to these factors, the designers must sacrifice either design schedule or test quality with standard logic BIST.

Fig. 1: Design flow for eliminating Xs before the place-and-route process.

Fig. 2: Design flow for eliminating Xs after the place-and-route process.

Fig. 3: Flow to handle unknown values in a design post-silicon.

An X-tolerant logic BIST, such as TestMAX XLBIST, enables designers to avoid these tradeoffs by minimizing the impact of Xs on test quality due to entire chain masking while also eliminating the need for design changes. Instead of masking the entire scan chain that causes high test coverage loss, TestMAX XLBIST can perform dynamic masking of scan cells containing Xs. Scan cell masking allows chain observability and achieves similar test time and coverage as an X-clean design for most scenarios without the associated overhead. TestMAX XLBIST achieves the test goals by intelligently using its PRPG re-seeding ability, dynamic X-tolerant decoder and X-masking decoding logic (shown in figure 4). Figure 5 shows an example comparison of test coverage versus pattern count for a given number of pattern seeds.

Fig. 4: TestMAX XLBIST architecture.

Fig. 5: TestMAX XLBIST achieves high coverage with multiple seeds.

In addition to test time and coverage requirements, ICs used in safety-critical applications also require testing at different stages of their functional operation to ensure early detection and mitigation of any potential defects and their impact. TestMAX XLBIST supports three main phases of in-system test: power-on system test (POST), test during functional operation and power-off system test. TestMAX XLBIST architecture is also designed to support deterministic test pattern generation for manufacturing test which eliminates the need for a separate codec logic when a chip requires both manufacturing and in-system test. In addition to its X-tolerance capability, TestMAX XLBIST also can generate hardware to enable power-aware patterns for both in-system test and manufacturing test. It also supports in-system test patterns based on advanced fault models including cell-aware, path-delay and transition.

In today’s competitive landscape full of complex designs, designers cannot afford to compromise between design schedule and test quality of ICs, especially in safety-critical applications. Achieving an X-clean design by going through design change iterations or adding more test patterns as required by standard LBIST in order to meet test goals is not an acceptable solution. TestMAX XLBIST performs optimally on X-clean designs while also providing the ability to handle designs with X values without needing to change the design or masking entire scan chains, meeting both design schedule and test quality goals.

Giri Podichetty is a product marketing director in Synopsys’ Digital Design Group.

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