Use Inference Benchmarks Similar To Your Application


If an Inference IP supplier or Inference Accelerator Chip supplier offers a benchmark, it is probably ResNet-50. As a result, it might seem logical to use ResNet-50 to compare inference offerings. If you plan to use ResNet-50 it would be; but if your target application model is significantly different from Resnet-50 it could lead you to pick an inference offering that is not best for you. ... » read more

Lies, Damn Lies, And TOPS/Watt


There are almost a dozen vendors promoting inferencing IP, but none of them gives even a ResNet-50 benchmark. The only information they state typically is TOPS (Tera-Operations/Second) and TOPS/Watt. These two indicators of performance and power efficiency are almost useless by themselves. So what, exactly, does X TOPS really tell you about performance for your application? When a vendor ... » read more

High Neural Inferencing Throughput At Batch=1


Microsoft presented the following slide as part of their Brainwave presentation at Hot Chips this summer: In existing inferencing solutions, high throughput (and high % utilization of the hardware) is possible for large batch sizes: this means that instead of processing say one image at a time, the inferencing engine processes say 10 or 50 images in parallel. This minimizes the number of... » read more

Real-Time Object Recognition At Low Cost/Power/Latency


Most neural network chips and IP talk about ResNet-50 benchmarks (image classification at 224x224 pixels). But we find that the number one neural network of interest for most customers is real-time object recognition, such as YOLOv3. It's not possible to do comparisons here because nobody shows a YOLOv3 benchmark for their inferencing. But it's very possible to improve on the inferencing per... » read more

Reconfigurable eFPGA For Aerospace Applications


Market research reports indicate about 10% of all dollar revenue of FPGA chips is for use in aerospace applications, and DARPA/DoD reports indicate about one-third of all dollar volume of ICs purchased by U.S. aerospace are FPGAs. FPGAs clearly are very important for aerospace applications because of a combination of short development time and the long mission life of many aerospace applica... » read more

Flexible, Energy-Efficient Neural Network Processing At 16nm


At Hot Chips 30, held in August in Silicon Valley, Harvard University (Paul Whatmough, SK Lee, S Xi, U Gupta, L Pentecost, M Donato, HC Hseuh, Professor Brooks and Professor Gu) made a presentation on “SMIV: A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IOT Devices. ” (Their complete presentation is available now on the Hot Chips website for attendees and will be p... » read more

Sandia Labs’ New Configurable SoC


At DAC 2018, held in June in San Francisco, Sandia Labs made a public presentation for the first time describing its first SoC using eFPGA, called Dragonfly. This is the first public disclosure by any organization describing its requirements, architecture and use cases for the new technology option of embedded FPGA. John Teifel led the project for Sandia National Laboratories. Sandia has ... » read more

Reconfigurable AI Building Blocks For SoCs And MCUs


FPGA chips are in use in many AI applications today, including Cloud datacenters. Embedded FPGA (eFPGA) is now becoming used for AI applications as well. Our first public customer doing AI with EFLX eFPGA is Harvard University, who will present a paper at Hot Chips August 20th on Edge AI processing using EFLX: "A 16nm SoC with Efficient and Flexible DNN Acceleration for Intelligent IoT Devi... » read more

Architects: How To Get The Most Out Of eFPGA


At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA. 1. Use as little eFPGA a... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

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