Architects: How To Get The Most Out Of eFPGA


At Flex Logix, we are working with customers with a wide range of applications: MCU, IoT, SoC, Networking, Wireless Base Station, Communications, Data Center, AI, Vision, Signal Processing and Aerospace. Their needs and their situations are all very different, but we have noticed some common learnings across the range of applications as people learn how to use eFPGA. 1. Use as little eFPGA a... » read more

Timing Signoff Methodology For eFPGA


An eFPGA is a hard IP block in an SoC. Most SoCs are made up of a collection of hard IP blocks (RAM, SerDes, PHYs…) and the remaining logic is constructed using Standard Cells. The timing signoff for an eFPGA’s interface with the rest of the chip is designed to leverage standard ASIC timing signoff flow for a hard-macro: as long as inputs/output to/from the eFPGA are all flopped, the int... » read more

Introduction To eFPGA Software


In February, we covered “Introduction to eFPGA Hardware.” Now in April, we’ll provide an introduction to eFPGA software. An eFPGA is a block of programmable logic from a few thousand to a few hundred thousand LUTs (look up tables) of programmable logic that is embedded in an SoC. The clock(s) for the eFPGA come from the SoC. The configuration of the eFPGA is done by the SoC... » read more

eFPGA: Think Differently & Experiment


New technologies are never overnight successes and usually develop in new applications. Arm and other embedded processors today are a huge success and pervasive in almost all chips. It took Arm more than five years to win the first five customers. The first applications were not competitive with Intel’s PC dominance but instead filled needs in emerging applications such as mobile phones an... » read more

Introduction To eFPGA Hardware


Intel builds processor chips and Arm provides processor cores to integrate into chips. Xilinx and Intel (nee Altera) build FPGAs and a range of new startups provide embedded FPGA (eFPGA) to integrate into chips: Achronix, Flex Logix, Menta and QuickLogic. As the diagram above shows, an FPGA chip is a core (the “fabric”) which is surrounded by various kinds of I/O including SERDES,... » read more

The Importance Of Metal Stack Compatibility For Semi IP


Architects and front end designers usually leave the back end to the physical designers: they know there can be different numbers of metal layers, but may not realize the characteristics of each metal layer may vary layer by layer as well and that different chips use different metal stack ups to optimize for their requirements. This slide from IDF14 shows a simple summary of the breadth of v... » read more

Get eFPGA With Your CPU Now


eFPGA is available now on mainstream process nodes (40, 28 and 16), in sizes from 200 LUTs to 200K LUTs and with options for DSP and RAM integration to fit almost any customer need. Flex Logix has been working for some time with multiple customers on integrating eFPGA with their CPUs: ARM, RISC-V, Tensilica and others. Bus interfaces include AXI, AHB, APB and TL. Our lead customer has workin... » read more

New Interconnect Makes eFPGA Dense And Portable


FPGAs were invented over 30 years ago. Today they are much bigger and faster, but their basic architecture remains unchanged: logic blocks formed around LUTs (look-up-tables) in a sea of mesh (x/y grid) interconnect with a matrix of switches at every “intersection.” One FPGA company executive once said they don’t really sell programmable logic, they sell programmable interconnect, beca... » read more