Interconnect Prominence In Fail-Operational Architectures

By Kurt Shuler - 02 May, 2019 - Comments: 0

When we in the semiconductor world think about safety, we think about ISO 26262, FMEDA and safety mechanisms like redundancy, ECC and lock-step operation. Once we have that covered, any other aspect of safety is somebody else’s problem, right? Sadly no, for us at least. As we push towards higher levels of autonomy, SAE levels 3 and above, we’re integrating more functionality into our SoCs, ... » read more

Memory Architectures In AI: One Size Doesn’t Fit All

By Kurt Shuler - 04 Apr, 2019 - Comments: 0

In the world of regular computing, we are used to certain ways of architecting for memory access to meet latency, bandwidth and power goals. These have evolved over many years to give us the multiple layers of caching and hardware cache-coherency management schemes which are now so familiar. Machine learning (ML) has introduced new complications in this area for multiple reasons. AI/ML chips ca... » read more

AI: Where’s The Money?

By Kurt Shuler - 07 Mar, 2019 - Comments: 0

A one-time technology outcast, Artificial Intelligence (AI) has come a long way. Now there’s groundswell of interest and investments in products and technologies to deliver high performance visual recognition, matching or besting human skills. Equally, speech and audio recognition are becoming more common and we’re even starting to see more specialized applications such as finding optimized... » read more

ISO 26262:2018, 2nd Edition: What Changes?

By Kurt Shuler - 07 Feb, 2019 - Comments: 0

If you’re involved somehow in design for automotive electronics, you probably have more than a cursory understanding of the ISO 26262 standard. What your organization is working from is most likely the 2011 definition. The most recent update is formally known as ISO 26262:2018, less formally as ISO 26262 2nd Edition. Figure 1. Overview of the ISO 26262:2018 series of standards (Source IS... » read more

AI Chips: NoC Interconnect IP Solves Three Design Challenges

By Kurt Shuler - 10 Jan, 2019 - Comments: 0

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of the FlexNoC interconnect IP with a new optional AI package. The novel NoC interconnect technologies solves many data flow problems in today’s AI designs. Innovative features address the requirements of the next-generation of AI chips t... » read more

A Primer On Last-Level Cache Memory For SoC Designs

By Kurt Shuler - 06 Sep, 2018 - Comments: 0

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver assistance systems (ADAS), machine learning, and data-center applications. LLC is a standalone memory that inserts cache between functional blocks and external memory to ease conflicting requireme... » read more

Artificial Intelligence Chips: Past, Present and Future

By Ty Garibay - 02 Aug, 2018 - Comments: 0

Artificial Intelligence (AI) is much in the news these days. AI is making medical diagnoses, synthesizing new chemicals, identifying the faces of criminals in a huge crowd, driving cars, and even creating new works of art. Sometimes it seems as if there is nothing that AI cannot do and that we will all soon be out of our jobs, watching the AIs do everything for us. To understand the origins ... » read more

Not Enough Respect For SoC Interconnect

By K. Charles Janac - 30 Jul, 2018 - Comments: 0

For high-volume system-on-chip (SoC) applications—artificial intelligence (AI), automotive, mobility, solid state drives and more—effective interconnect technology can generate hundreds of millions of dollars in revenue due to smaller chip area, better functionality and faster delivery of SoC platforms. State-of-the-art interconnect technology also allows chip designers to create SoC deriva... » read more

Neural Nets In ADAS And Autonomous Driving SoC Designs

By Kurt Shuler - 26 Apr, 2018 - Comments: 0

Automotive electronics has ushered in a new wave of semiconductor design innovation and one new technology gaining a lot of attention is neural networks (NNs). Advanced driving assistance systems (ADAS) and autonomous car designs now rely on NNs to meet the real-time requirements of complex object-recognition algorithms. The concept of NNs has been around since World War II, promising a futu... » read more

How SoC Interconnect Enables Flexible Architecture For ADAS And Autonomous Car Designs

By Kurt Shuler - 22 Feb, 2018 - Comments: 0

When the mobile phone era saw its fastest growth, the design teams that were the most innovative were able to introduce game-changing features before anyone else. Those companies also had the most configurable interconnect IP, allowing them to adapt to quickly changing market needs faster than their competition. Now, nearly a decade later, when autonomous driving is quickly moving into the m... » read more

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Knowledge Centers
Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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