category: Blogs – SLD

category: IoT, Security & Automotive

DAC 2019 Was About More Than Just Chips
By Jo Windel - 27 Jun, 2019 - Comments: 0

Behind all the noise of the vast array of slot machines, gambling tables and bars and the bright lights of the Las Vegas strip was the large gathering of the annual Design Automation Conference, which was back in the bustling city for the first time in just under 20 years. Following its success in San Francisco last year, and indeed where it will return next July (co-located with the SEMICON... » read more

Meanwhile, 35 Years Later…
By Zibi Zalewski - 27 Jun, 2019 - Comments: 0

At this year’s Design Automation Conference, held on June 3, 4 and 5 in Las Vegas and about 10 miles away from our head office in Las Vegas, Nevada, we celebrated our 35th anniversary with a resounding reaffirmation of our raison d’etre: the provision of verification solutions for some of industry’s most pressing challenges. We had on display a variety of solutions – both hardware ... » read more

Cyber Attacks Against Vehicles On The Rise
By Aileen Ryan - 03 Jun, 2019 - Comments: 0

Who is worried about automotive security and safety? I, for one, most definitely am! I’ve written previously about how tackling this problem makes good business sense. But the more immersed I become in this topic, the more I feel personally concerned about the implications of this, and the snail’s-pace at which the market is responding to it. I’ve just read an Upstream Security repo... » read more

FPGA And System Designs Get To Market Faster Leveraging ASIC-Proven Analysis Tools
By Chris Giles - 30 May, 2019 - Comments: 0

Increasing power constraints have resulted in finer-grained partitioning of designs into functional domains that can have clocks disabled or, more drastically, are powered down entirely. Systems are required to adaptively manage clocks to minimize switching power. Performance and area constraints have led to the abandonment of more conservative practices in favor of more aggressive designs; ... » read more

Shift-Left Low Power Verification With UPF Information Model
By Himanshu Bhatt - 30 May, 2019 - Comments: 0

By Himanshu Bhatt, Shreedhar Ramachandra and Narayanan Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the factors limiting the users from writing re-usable low power testbenches that can monitor the UPF objects and react to the state changes of UPF objects. To meet this requirement for the user to... » read more

Intellectual Property: Trust… But Verify
By John Hallman - 30 May, 2019 - Comments: 0

For those around the microelectronic component industry for many years, we have seen quite a transformation of capability, sourcing of the supply chain, and now threats to these devices that drive the technology in our world today. These integrated circuits (ICs), once so simple as a few transistors, have continued to follow Moore’s Law and are now made up of tens of billions of transistor... » read more

Delivering High-Speed Communications: The Back Story
By Mike Gianfagna - 30 May, 2019 - Comments: 0

Back in January, I posted a blog about what it takes to deliver high-speed communication. In that post, I talked about a new test board for our high-speed 7nm 56G PAM4 & NRZ DSP-based long-reach SerDes. We collaborated with several companies to build a high-precision board that could be used to test our SerDes in a system context. At that time, we were just finishing the opening act for thi... » read more

The Changing Landscape of Hardware-Based Verification And Software Development
By Frank Schirrmeister - 24 May, 2019 - Comments: 0

As the EDA is gearing up for its biggest industry event, the Design Automation Conference (DAC), this year in Las Vegas, it is interesting to observe what is going on in hardware-based development of emulation and prototyping. The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have only grown stronger and are causing changes in the development landsc... » read more

Interconnect Prominence In Fail-Operational Architectures
By Kurt Shuler - 02 May, 2019 - Comments: 0

When we in the semiconductor world think about safety, we think about ISO 26262, FMEDA and safety mechanisms like redundancy, ECC and lock-step operation. Once we have that covered, any other aspect of safety is somebody else’s problem, right? Sadly no, for us at least. As we push towards higher levels of autonomy, SAE levels 3 and above, we’re integrating more functionality into our SoCs, ... » read more

Challenges In Using HLS For FPGA Design
By Loren Hobbs - 29 Apr, 2019 - Comments: 0

High-level synthesis (HLS) tools, which transform C/C++ source code to Verilog/VHDL, have been commercially available for over 15 years. HLS tools from FPGA vendors and EDA companies promise improved productivity through a higher-level of abstraction, faster verification and quicker design iterations. For example, simulating your design in C/C++ can be 10 to 100x faster than simulating in RTL (... » read more

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