How To Plan And Conduct Highly Accelerated Life Testing


Assessing the robustness of an electronic product is integral to successful design and performance. Highly accelerated life testing (HALT) is an important testing tool for this purpose, and its effectiveness can be maximized through careful planning prior to setup and detailed execution. What is HALT? HALT is the process of applying increased stressors to an electronic device to force failure... » read more

Transitioning To Photonics


Silicon photonics is undergoing a resurgence as traditional approaches for reducing power and heat become more difficult and expensive, opening the door to a whole new set of technological challenges and driving up demand for a skill set that is in short supply today. From a technology standpoint, photonics is extremely complex. Signals drift, they are modulated with heat, and structures lik... » read more

How eMRAM Addresses The Power Dilemma In Advanced-Node SoCs


By Rahul Thukral and Bhavana Chaurasia Our intelligent, interconnected, data-driven world demands more computation and capacity. Consider the variety of smart applications we now have. Cars can transport passengers to their destinations using local and remote AI decision-making. Robot vacuum cleaners keep our homes tidy, and smartwatches can detect a fall and call emergency services. With hi... » read more

Nightmare Fuel: The Hazards Of ML Hardware Accelerators


A major design challenge facing numerous silicon design teams in 2023 is building the right amount of machine learning (ML) performance capability into today’s silicon tape out in anticipation of what the state of the art (SOTA) ML inference models will look like in 2026 and beyond when that silicon will be used in devices in volume production. Given the continuing rapid rate of change in mac... » read more

DDR5 Memory Enables Next-Generation Computing


Computing main memory transitions may only happen once a decade, but when they do, it is a very exciting time in the industry. When JEDEC announced the publication of the JESD79-5 DDR5 SDRAM standard in 2021, it signaled the beginning of the transition to DDR5 server and client dual-inline memory modules (Server RDIMMs, Client UDIMMs and SODIMMs). We are now firmly on this path of enabling the ... » read more

Unblocking The Full Potential Of PCIe Gen6 With Shared Flow Control


As technology advances at a rapid pace, PCI Express (or PCIe) has grown tremendously, allowing data transfer up to 64 GT/s in Gen6. This technology is widely used in data centers, artificial intelligence and machine learning computing, high-performance computing accelerators, and high-speed applications—including high-end SSDs, automotive, IoT, and mil-aero. To fully utilize this high-spee... » read more

Introducing Device Virtualization Principles For Real-Time Systems


The rising market share of electric vehicles and the reduction in combustion engines required in the future is transforming the automotive industry. One could think this would lead to a simplification in vehicle design, but with driver assistance technologies becoming a key differentiator, they are in fact becoming real "data centers on wheels." Furthermore, car drivers are used to a consumer-b... » read more

Printing Grids In 3D


Those of you who attended the 2011 Pointwise User Group Meeting may remember that our company president, John Chawner, mentioned during his closing statements how nice it would be to have the ability to print your grids in 3D. That was more than just a dreamy, "what if" statement. It is a reality! Almost. A little history 3D-printed F-16 forward fuselage. I have always been fascinat... » read more

RISC-V Driving New Verification Concepts


Semiconductor Engineering sat down to discuss gaps in tools and why new methodologies are needed for RISC-V processors, with Pete Hardee, group director for product management at Cadence; Mike Eftimakis, vice president for strategy and ecosystem at Codasip; Simon Davidmann, founder and CEO of Imperas Software; Sven Beyer, program manager for processor verification at Siemens EDA; Kiran Vittal, ... » read more

Effective Resource Utilization In PCIe Gen6: Shared Flow Control


In PCIe 6.0, the data rate has doubled from 32 GT/s to 64 GT/s. This technology is a cost-effective and scalable interconnect solution that will continue to impact data-intensive markets and applications while maintaining backward compatibility with all previous generations of PCIe. Data-intensive uses include data centers, artificial intelligence/machine learning computing, high-performance co... » read more

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