Precision Patterning Options Emerge For Advanced Packaging

By Gregory Haley - 23 Jul, 2024 - Comments: 0

The chip industry is ratcheting up investments in advanced packaging as it strives to keep pace with demands for increased functionality and higher performance, including novel patterning technologies that can reduce costs and speed time to market. Success in advanced packages is partly dependent on effectively managing the interconnectivity between the chips, which requires increasingly pre... » read more

Improving Line Edge Roughness Using Virtual Fabrication

By Qingpeng Wang - 23 Jul, 2024 - Comments: 0

Line edge roughness (LER) is a variation in the width of a lithographic pattern along one edge of a structure inside a chip. Line edge roughness can be a critical variation source and defect mechanism in advanced logic and memory devices and can lead to poor device performance or even device failure. [1~3]. Deposition-etch cycling is an effective technique to reduce line edge roughness. In this... » read more

Reliability Performance Of S-Connect Module (Bridge Technology) For Heterogeneous Integration Packaging

By Heejun Jang - 23 Jul, 2024 - Comments: 0

With the explosive increase in demand for artificial intelligence (AI), autonomous driving, Internet of Things (IoT), data centers, augmented reality and virtual reality (AR/VR), the market of high-performance computing (HPC) applications is growing rapidly [2]. And, the HPC market requires high processing speed, fast network clusters and large parallel computing. To meet the market requirement... » read more

Metrology Analysis Tool For Photolithography Process Characterization At Advanced Nodes

By Wolfgang Demmerle - 23 Jul, 2024 - Comments: 0

Continued scaling of integrated circuits to smaller dimensions is still a viable way to increase compute power, achieve higher memory cell density, or reduce power consumption. These days, chip makers are using single-digit nanometer figures or even Angstrom to label their manufacturing technology nodes, which are associated with the size of features patterned during the lithography process. ... » read more

European Mask And Lithography Conference 2024 Worth Attending

By Asmus Hetzel - 23 Jul, 2024 - Comments: 0

The European Mask and Lithography Conference (EMLC) 2024 recently was held in Grenoble, France, and had about 190 participants from a wide range of companies and institutions. Being relatively new to the field of lithography (my background is EDA, machine learning, optimization) and not being a fan of gigantic conferences, I thought it would be a good idea to visit this conference. My main p... » read more

CD Spec For Curvilinear Masks

By D2S - 23 Jul, 2024 - Comments: 0

Within the photomask industry, there's a major transformation from conventional Manhattan masks to more advanced curvilinear masks. Researchers from D2S and Micron Technology propose an equivalent CD spec for the curvy masks and use this spec to show that curvy masks have smaller mask variations than Manhattan masks. Find the technical paper here. Published June 2024. Linyong (Leo) Pang, ... » read more

New Interconnect Metals Need New Dielectrics

By Katherine Derbyshire - 23 Jul, 2024 - Comments: 0

Just as circuit metallization must evolve to manage resistance as features shrink, so must the dielectric half of the interconnect stack. For quite some time, manufacturers have needed a dielectric constant (k) less than 4, which is the value for SiO2, but they have struggled to find materials that combine a low dielectric constant with mechanical and chemical stability. In work presented at... » read more

Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding

By Brewer Science - 23 Jul, 2024 - Comments: 0

A technical paper titled "Multi-tier Die Stacking Through Collective Die-to-Wafer Hybrid bonding" was published by researchers at imec, Brewer Science and SUSS MicroTec Lithography GmbH. Abstract "A collective die-to-wafer bonding flow is extended beyond the N=2 tier to the N=3 and N=4 tier by collectively bonding multiple layers of dies on top of a target wafer. The N=2 die-level is show... » read more

Building A Sustainable And Diverse Semiconductor Workforce: Insights From ASMC 2024 Panel Discussion

By Krish Raghunath - 23 Jul, 2024 - Comments: 0

As the semiconductor industry works to attract talent to overcome its labor shortage, governments, educators, and the private sector must collaborate to make industry career opportunities more accessible for prospective employees. This concept provided the framework for a panel discussion during SEMI’s 35th annual Advanced Semiconductor Manufacturing Conference (ASMC) that took place in Alba... » read more

Intel Vs. Samsung Vs. TSMC

By Ed Sperling - 15 Jul, 2024 - Comments: 3

The three leading-edge foundries — Intel, Samsung, and TSMC — have started filling in some key pieces in their roadmaps, adding aggressive delivery dates for future generations of chip technology and setting the stage for significant improvements in performance with faster delivery time for custom designs. Unlike in the past, when a single industry roadmap dictated how to get to the next... » read more

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Entities, people and technologies explored

Shift Left Is The Tip Of The Iceberg

A transformative change is underway for semiconductor design and EDA. New languages, models, and abstractions will need to be created.

by Brian Bailey

Partitioning In The Chiplet Era

Understanding how chiplets interact under different workloads is critical to ensuring signal integrity and optimal performance in heterogeneous designs.

by Ann Mutschler

3.5D: The Great Compromise

Pros and cons of a middle-ground chiplet assembly that combines 2.5D and 3D-IC.

by Ed Sperling

AI’s Role In Chip Design Widens, Drawing In New Startups

Focus is on letting engineers do much more with the same or fewer resources — and less drudgery.

by Karen Heyman

Key Technologies To Extend EUV To 14 Angstroms

Alongside high-NA EUV will be better-performing photoresists, reduced roughness using passivation and etch, and lateral etching to reduce tip-to-tip dimensions.

by Laura Peters

What Comes After HBM For Chiplets

The standard for high-bandwidth memory limits design freedom at many levels, but that is required for interoperability. What freedoms can be taken from other functions to make chiplets possible?

by Brian Bailey

Memory Fundamentals For Engineers

eBook: Nearly everything you need to know about memory, including detailed explanations of the different types of memory; how and where these are used today; what's changing, which memories are successful and which ones might be in the future; and the limitations of each memory type.

by The SE Staff

Why Small Fab And Assembly Houses Are Thriving

Megafabs churning out the most advanced processors are not the only game in town.

by Bryon Moyer

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