Redefining Backside Metallization: Low‑Temperature Solutions For HDFO And S‑SWIFT Designs


As chip performance and integration continue to advance, thermal dissipation control has become increasingly critical not only at the wafer fabrication level but also in the packaging industry. For artificial intelligence (AI) and high performance computing (HPC) applications, the industry is gradually shifting toward 2.5D integration. In response to the growing demand, High-Density Fan-Out (HD... » read more

Understanding Within-Wafer Variations: A Virtual Fabrication Approach


One of the unavoidable aspects of chip manufacturing is that some dies on a wafer perform differently than others, even though they were made together on the same wafer. This blog dives into that mystery and provides a way to predict and fix these issues. Imagine baking cookies. If your oven has hot and cold spots, some cookies will be perfect; others burnt. That’s what happens in chip man... » read more

Force Fields Will Accelerate Atomistic Simulations By 10,000× In 2026, Unlocking New Era Of Discovery


By Anders Blom and Igor Markov “Force fields” have long captured our imagination — the invisible shields of science-fiction lore that protect starships and superheroes from harm. But in the world of scientific discovery, force fields play a much different role: They are mathematical models that let us peer into the atomic heart of matter itself. Now, thanks to breakthroughs in artif... » read more

Laser Arrays May Simplify Co-Packaged Optics


Key Takeaways Moving photonic ICs into the same package as silicon helps improve performance, but lasers remain outside. A new monolithic laser array allows hundreds of colors, each individually software-tunable New options are being turned into products, which could help commercialize CPO. The move to co-packaged optics (CPO) holds the promise of putting photonic ICs (PICs)... » read more

Leading At Light Speed: What Makes Photonics Leadership Different


By Jan-Bart Smits and David Harap Every time a transistor switches, it generates heat. Pack enough transistors together and you hit a wall: the chip melts before it computes. This thermal ceiling is why Splunk notes that "as physical and economic limitations are reached, the pace predicted by Moore's Law is slowing." Light solves this problem. Photons carry information without generating ... » read more

SEMI 2026 U.S. Policy Strategy


The semiconductor industry continues to serve as the foundation of U.S. technological innovation and economic growth, and it has entered its most decisive phase yet. As geopolitical competition intensifies and policy frameworks evolve, 2026 will push the United States to sustain its leadership in semiconductor design, manufacturing, and innovation amid growing alliances and accelerating competi... » read more

Why Indium Oxide Chips Are Getting So Much Attention


Key Takeaways Their low leakage is of interest for memory applications, particularly capacitor-less gain cell designs; They can be deposited over large areas using low-temperature processes, a very desirable characteristic for BEOL integration, and The variety of compositions available gives designers many options to achieve the specific properties they need. Indium tin oxide (ITO), ... » read more

When Cleaning Chips Isn’t Clean Enough


Key Takeaways Contamination is becoming much more difficult to identify at the most advanced nodes, forcing fabs to rethink how control is achieved. Issues may show up as electrical or statistical anomalies, not particles, and not at time zero. Reliable classification is needed to identify critical contamination and reduce time and effort spent on nuisance failures. For much... » read more

Enabling the Industry’s First GPU-Accelerated Manufacturing Platform


Discover how modern chip designs are revolutionizing the lithographic process, driving the need for innovative solutions to meet the industry's demand for shorter design cycles. This whitepaper explores the significant role of GPUs in accelerating computational lithography, offering unprecedented speed-ups for EDA tools in chip development. Learn about the collaborative efforts of Synopsys, NVI... » read more

Why Move To 2nm?


Key Takeaways: Scaling digital logic still provides significant benefits, especially lower power. Multi-die assemblies will be the predominant approach, and most of the circuitry will not be 2nm or below. While these systems are inherently more flexible, the number and complexity of tradeoffs required for optimizing PPA/C are increasing. The rollout of 2nm process nodes and ... » read more

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