HW Security: Multi-Agent AI Assistant Leveraging LLMs To Automate Key Stages of SoC Security Verification (U. of Florida)


A new technical paper titled "SV-LLM: An Agentic Approach for SoC Security Verification using Large Language Models" was published by researchers at University of Florida. Abstract "Ensuring the security of complex system-on-chips (SoCs) designs is a critical imperative, yet traditional verification techniques struggle to keep pace due to significant challenges in automation, scalability, c... » read more

Machine Intelligence on Wireless Edge Networks with RF Analog Architecture (MIT, Duke)


A new technical paper titled "Machine Intelligence on Wireless Edge Networks" was published by researchers at MIT and Duke University. Abstract "Deep neural network (DNN) inference on power-constrained edge devices is bottlenecked by costly weight storage and data movement. We introduce MIWEN, a radio-frequency (RF) analog architecture that "disaggregates" memory by streaming weights wirele... » read more

Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing (Infineon, U. Padova et al.)


A new technical paper titled "Domain Adaptation for Image Classification of Defects in Semiconductor Manufacturing" was published by researchers at Infineon Technologies, University of Padova and University of Bologna. Abstract "In the semiconductor sector, due to high demand but also strong and increasing competition, time to market and quality are key factors in securing significant marke... » read more

All-In-One Analog AI Accelerator With CMO/HfOx ReRAM Integrated Into The BEOL (IBM Research-Europe)


A new technical paper titled "All-in-One Analog AI Hardware: On-Chip Training and Inference with Conductive-Metal-Oxide/HfOx ReRAM Devices" was published by researchers at IBM Research-Europe. Abstract "Analog in-memory computing is an emerging paradigm designed to efficiently accelerate deep neural network workloads. Recent advancements have focused on either inference or training accelera... » read more

Review Paper: Wafer-Scale Accelerators Versus GPUs (UC Riverside)


A new technical paper titled "Performance, efficiency, and cost analysis of wafer-scale AI accelerators vs. single-chip GPUs" was published by researchers at UC Riverside. "This review compares wafer-scale AI accelerators and single-chip GPUs, examining performance, energy efficiency, and cost in high-performance AI applications. It highlights enabling technologies like TSMC’s chip-on-wafe... » read more

Fully Automated Hardware And Software Design Of Processor Chips (Chinese Academy Of Sciences)


A new technical paper titled "QiMeng: Fully Automated Hardware and Software Design for Processor Chip" was published by researchers at Chinese Academy of Sciences. Abstract "Processor chip design technology serves as a key frontier driving breakthroughs in computer science and related fields. With the rapid advancement of information technology, conventional design paradigms face three majo... » read more

Evaluation of LLMs on HDL-Based Communication Protocol Generation (U. of Illinois Urbana, CISPA)


A new technical paper titled "ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols" was published by researchers at University of Illinois Urbana Champaign and CISPA Helmholtz Center for Information Security. Abstract "Recent advances in Large Language Models (LLMs) have shown promising capabilities in generating code for general-purpose programming languages. ... » read more

PCM-Based IMC Technology: Overview Of Materials, Device Physics, Design and Fabrication (IBM Research-Europe)


A new technical paper titled "Phase-Change Memory for In-Memory Computing" was published by researchers at IBM Research-Europe. "We review the current state of phase-change materials, PCM device physics, and the design and fabrication of PCM-based IMC chips. We also provide an overview of the application landscape and offer insights into future developments," states the paper. Find the te... » read more

Hardware-Oriented Analysis of Multi-Head Latent Attention (MLA) in DeepSeek-V3 (KU Leuven)


A new technical paper titled "Hardware-Centric Analysis of DeepSeek's Multi-Head Latent Attention" was published by researchers at KU Leuven. Abstract "Multi-Head Latent Attention (MLA), introduced in DeepSeek-V2, improves the efficiency of large language models by projecting query, key, and value tensors into a compact latent space. This architectural change reduces the KV-cache size and s... » read more

Customizing An LLM Tailored Specifically For VHDL Code And Design Of High Performance Processors (IBM)


A new technical paper titled "Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors" was published by researchers at IBM. Abstract "The use of Large Language Models (LLMs) in hardware design has taken off in recent years, principally through its incorporation in tools that increase chip designer productivity. There has been considerable discussion about the ... » read more

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