Hyperscale HW Optimized Neural Architecture Search (Google)


A new technical paper titled "Hyperscale Hardware Optimized Neural Architecture Search" was published by researchers at Google, Apple, and Waymo. "This paper introduces the first Hyperscale Hardware Optimized Neural Architecture Search (H2O-NAS) to automatically design accurate and performant machine learning models tailored to the underlying hardware architecture. H2O-NAS consists of three ... » read more

Spiking Neural Networks: Hardware & Algorithm Developments


A new technical paper titled "Exploring Neuromorphic Computing Based on Spiking Neural Networks: Algorithms to Hardware" was published by researchers at Purdue University, Pennsylvania State University, and Yale University. Excerpt from Abstract: "In this article, we outline several strides that neuromorphic computing based on spiking neural networks (SNNs) has taken over the recent past, a... » read more

Digital Neuromorphic Processor: Algorithm-HW Co-design (imec / KU Leuven)


A technical paper titled "Open the box of digital neuromorphic processor: Towards effective algorithm-hardware co-design" was published by researchers at imec and KU Leuven. "In this work, we open the black box of the digital neuromorphic processor for algorithm designers by presenting the neuron processing instruction set and detailed energy consumption of the SENeCA neuromorphic architect... » read more

Scalable, Shared-L1-Memory Manycore RISC-V System


A new technical paper titled "MemPool: A Scalable Manycore Architecture with a Low-Latency Shared L1 Memory" was published by researchers at ETH Zurich and University of Bologna. Abstract: "Shared L1 memory clusters are a common architectural pattern (e.g., in GPGPUs) for building efficient and flexible multi-processing-element (PE) engines. However, it is a common belief that these tightly... » read more

Autonomous Driving: End-to-End Surround 3D Camera Perception System (NVIDIA)


A new technical paper titled "NVAutoNet: Fast and Accurate 360∘ 3D Visual Perception For Self Driving" was published by researchers at NVIDIA. Abstract "Robust real-time perception of 3D world is essential to the autonomous vehicle. We introduce an end-to-end surround camera perception system for self-driving. Our perception system is a novel multi-task, multi-camera network which takes a... » read more

Overview of Machine Learning Algorithms Used In Hardware Security (TU Delft)


A new technical paper titled "A Survey on Machine Learning in Hardware Security" was published by researchers at TU Delft. Abstract "Hardware security is currently a very influential domain, where each year countless works are published concerning attacks against hardware and countermeasures. A significant number of them use machine learning, which is proven to be very effective in ... » read more

Low-Power Heterogeneous Compute Cluster For TinyML DNN Inference And On-Chip Training


A new technical paper titled "DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training" was published by researchers at University of Bologna and ETH Zurich. Abstract "On-chip deep neural network (DNN) inference and training at the Extreme-Edge (TinyML) impose strict latency, throughput, accuracy, and flexibility requirements. Heterogeneous clus... » read more

Neuromorphic Computing: Self-Adapting HW With ReRAMs


A new technical paper titled "A self-adaptive hardware with resistive switching synapses for experience-based neurocomputing" was published by researchers at Infineon Technologies, Politecnico di Milano and IUNET, Weebit Nano, and CEA Leti. Abstract "Neurobiological systems continually interact with the surrounding environment to refine their behaviour toward the best possible reward. Achie... » read more

Combination of AI Techniques To Find The Best Ways to Place Transistors on Silicon Chips


A new technical paper titled "AutoDMP: Automated DREAMPlace-based Macro Placement" was published by researchers at NVIDIA. Abstract: "Macro placement is a critical very large-scale integration (VLSI) physical design problem that significantly impacts the design power-performance-area (PPA) metrics. This paper proposes AutoDMP, a methodology that leverages DREAMPlace, a GPU-accelerated place... » read more

3D-IC: Operator Learning Framework For Ultra-Fast 3D Chip Thermal Prediction Under Multiple Chip Design Configurations


A new technical paper titled "DeepOHeat: Operator Learning-based Ultra-fast Thermal Simulation in 3D-IC Design" was published (preprint) by researchers at UCSB and Cadence. Abstract "Thermal issue is a major concern in 3D integrated circuit (IC) design. Thermal optimization of 3D IC often requires massive expensive PDE simulations. Neural network-based thermal prediction models can perform ... » read more

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