SB MOSFET-Based Ultra-Low Power Real-Time Neurons for Neuromorphic Computing (Indian Institute of Technology)


A technical paper titled “Schottky Barrier MOSFET Enabled Ultra-Low Power Real-Time Neuron for Neuromorphic Computing” was published by researchers at the Indian Institute of Technology (IIT) Bombay. Abstract: "Energy-efficient real-time synapses and neurons are essential to enable large-scale neuromorphic computing. In this paper, we propose and demonstrate the Schottky-Barrier MOSFE... » read more

Chiplets: Bridging The Gap Between The System Requirements And Design Aggregation, Planning, And Optimization


A technical paper titled “System and Design Technology Co-optimization of Chiplet-based AI Accelerator with Machine Learning” was published by researchers at Auburn University. Abstract: "With the availability of advanced packaging technology and its attractive features, the chiplet-based architecture has gained traction among chip designers. The large design space and the lack of sys... » read more

Object Detection CNN Suitable For Edge Processors With Limited Memory


A technical paper titled “TinyissimoYOLO: A Quantized, Low-Memory Footprint, TinyML Object Detection Network for Low Power Microcontrollers” was published by researchers at ETH Zurich. Abstract: "This paper introduces a highly flexible, quantized, memory-efficient, and ultra-lightweight object detection network, called TinyissimoYOLO. It aims to enable object detection on microcontrol... » read more

A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip


A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Comparing Analog and Digital SRAM In-Memory Computing Architectures (KU Leuven)


A technical paper titled "Benchmarking and modeling of analog and digital SRAM in-memory computing architectures" was published by researchers at KU Leuven. Abstract: "In-memory-computing is emerging as an efficient hardware paradigm for deep neural network accelerators at the edge, enabling to break the memory wall and exploit massive computational parallelism. Two design models have surge... » read more

Issues and Opportunities in Using LLMs for Hardware Design


A technical paper titled "Chip-Chat: Challenges and Opportunities in Conversational Hardware Design" was published by researchers at NYU and University of New South Wales. Abstract "Modern hardware design starts with specifications provided in natural language. These are then translated by hardware engineers into appropriate Hardware Description Languages (HDLs) such as Verilog before syn... » read more

Optimizing Projected PCM for Analog Computing-In-Memory Inferencing (IBM)


A new technical paper titled "Optimization of Projected Phase Change Memory for Analog In-Memory Computing Inference" was published by researchers at IBM Research. "A systematic study of the electrical properties-including resistance values, memory window, resistance drift, read noise, and their impact on the accuracy of large neural networks of various types and with tens of millions of wei... » read more

Solving Memory Mapping Issues with Deep RL (Google)


A technical paper titled "Optimizing Memory Mapping Using Deep Reinforcement Learning" was published by Google DeepMind and Google. Abstract: "Resource scheduling and allocation is a critical component of many high impact systems ranging from congestion control to cloud computing. Finding more optimal solutions to these problems often has significant impact on resource and time savings, red... » read more

RL-Guided Detailed Routing Framework for Advanced Custom Circuits


A technical paper titled "Reinforcement Learning Guided Detailed Routing for Custom Circuits" was published by researchers at UT Austin, Princeton University, and NVIDIA. "This paper presents a novel detailed routing framework for custom circuits that leverages deep reinforcement learning to optimize routing patterns while considering custom routing constraints and industrial design rules. C... » read more

Cross-Shaped Reconfigurable Transistor (CS-RFET) With Flexible Signal Routing


A new technical paper titled "Cross-Shape Reconfigurable Field Effect Transistor for Flexible Signal Routing" was published by researchers at NaMLab gGmbH, École Centrale de Lyon, and TU Dresden. "A detailed comprehensive study of the cross-shape reconfigurable field effect transistor electrical characteristics are presented. The fabricated device demonstrates nearly equal transistor charac... » read more

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