category: Architectures

category: IoT, Security & Automotive

A Formal Verification Method To Detect Timing Side Channels In MCU SoCs
By Technical Paper Link - 11 Oct, 2023 - Comments: 0

A technical paper titled “A New Security Threat in MCUs – SoC-wide timing side channels and how to find them” was published by researchers at University of Kaiserslautern-Landau and Stanford University. Abstract: "Microarchitectural timing side channels have been thoroughly investigated as a security threat in hardware designs featuring shared buffers (e.g., caches) and/or parallelism b... » read more

LLM-Aided AI Accelerator Design Automation (Georgia Tech)
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models” was published by researchers at Georgia Institute of Technology. Abstract: "The remarkable capabilities and intricate nature of Artificial Intelligence (AI) have dramatically escalated the imperative for specialized AI accelerators. Nonetheless, designing these accele... » read more

Neuromorphic Hardware Accelerator For Heterogeneous Many-Accelerator SoCs
By Technical Paper Link - 28 Sep, 2023 - Comments: 0

A technical paper titled “SpikeHard: Efficiency-Driven Neuromorphic Hardware for Heterogeneous Systems-on-Chip” was published by researchers at Columbia University. Abstract: "Neuromorphic computing is an emerging field with the potential to offer performance and energy-efficiency gains over traditional machine learning approaches. Most neuromorphic hardware, however, has been designed wi... » read more

SRAM-Based IMC For Cryogenic CMOS Using Commercial 5 nm FinFETs
By Technical Paper Link - 27 Sep, 2023 - Comments: 0

A technical paper titled “Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs” was published by researchers at University of Stuttgart, Indian Institute of Technology Kanpur, University of California Berkeley, and Technical University of Munich. Abstract: "Cryogenic CMOS circuits that efficiently connect the classical domain with the quantum world are the co... » read more

Photonic-Electronic SmartNIC With Fast and Energy-Efficient Photonic Computing Cores (MIT)
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “Lightning: A Reconfigurable Photonic-Electronic SmartNIC for Fast and Energy-Efficient Inference” was published by researchers at Massachusetts Institute of Technology (MIT). Abstract: "The massive growth of machine learning-based applications and the end of Moore's law have created a pressing need to redesign computing platforms. We propose Lightning, the first ... » read more

3D-Integrated Neuromorphic Hardware With A Two-Level Neuromorphic “Synapse Over Neuron” Structure
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “3D Neuromorphic Hardware with Single Thin-Film Transistor Synapses Over Single Thin-Body Transistor Neurons by Monolithic Vertical Integration” was published by researchers at Korea Advanced Institute of Science and Technology (KAIST) and SK hynix. Abstract: "Neuromorphic hardware with a spiking neural network (SNN) can significantly enhance the energy efficiency... » read more

Applying a Floating Gate Field Effect Transistor To A Logic-in-Memory Application Circuit Design
By Technical Paper Link - 19 Sep, 2023 - Comments: 0

A technical paper titled “Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET)” was published by researchers at Konkuk University, Korea National University of Transportation, Samsung Electronics, and Sungkyunkwan University. Abstract: "The high data throughput and high energy efficiency required recently are increasingly difficult to implement... » read more

Hardware Platform For Evolving Robots
By Technical Paper Link - 15 Sep, 2023 - Comments: 0

A technical paper titled “Practical hardware for evolvable robots” was published by researchers at University of York, Edinburgh Napier University, Vrije Universiteit Amsterdam, University of the West of England, and University of Sunderland. Abstract: "The evolutionary robotics field offers the possibility of autonomously generating robots that are adapted to desired tasks by iteratively... » read more

A Hierarchical Instruction Cache Tailored To Ultra-Low-Power Tightly-Coupled Processor Clusters
By Technical Paper Link - 15 Sep, 2023 - Comments: 0

A technical paper titled “Scalable Hierarchical Instruction Cache for Ultra-Low-Power Processors Clusters” was published by researchers at University of Bologna, ETH Zurich, and GreenWaves Technologies. Abstract: "High Performance and Energy Efficiency are critical requirements for Internet of Things (IoT) end-nodes. Exploiting tightly-coupled clusters of programmable processors (CMPs) ha... » read more

SG2042 64-Core RISC-V CPU Versus Existing RISC-V HW And High Performance x86 CPUs
By Technical Paper Link - 13 Sep, 2023 - Comments: 0

A technical paper titled “Is RISC-V ready for HPC prime-time: Evaluating the 64-core Sophon SG2042 RISC-V CPU” was published by researchers at University of Edinburgh. Abstract: "The Sophon SG2042 is the world's first commodity 64-core RISC-V CPU for high performance workloads and an important question is whether the SG2042 has the potential to encourage the HPC community to embrace RISC-... » read more

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