category: Architectures

category: IoT, Security & Automotive

Neuromorphic Artificial Synaptic Device Combining Memristor Arrays With Copper Iodide
By Technical Paper Link - 13 Sep, 2023 - Comments: 0

A technical paper titled “Charge-Mediated Copper-Iodide-Based Artificial Synaptic Device with Ultrahigh Neuromorphic Efficacy” was published by researchers at University of Glasgow, City University of Hong Kong, and Hong Kong Metropolitan University. Abstract: "In the realm of artificial intelligence, ultrahigh-performance neuromorphic computing plays a significant role in executing multi... » read more

A Microfluidics Device That Can Perform ANN Computation On Data Stored In DNA
By Technical Paper Link - 06 Sep, 2023 - Comments: 0

A technical paper titled “Neural network execution using nicked DNA and microfluidics” was published by researchers at University of Minnesota Twin-Cities and Rochester Institute of Technology. Abstract: "DNA has been discussed as a potential medium for data storage. Potentially it could be denser, could consume less energy, and could be more durable than conventional storage media such a... » read more

An Energy-Efficient 10T SRAM In-Memory Computing Macro Architecture For AI Edge Processor
By Technical Paper Link - 28 Aug, 2023 - Comments: 0

A technical paper titled “An energy-efficient 10T SRAM in-memory computing macro for artificial intelligence edge processor” was published by researchers at Atal Bihari Vajpayee-Indian Institute of Information Technology and Management (ABV-IIITM). Abstract: "In-Memory Computing (IMC) is emerging as a new paradigm to address the von-Neumann bottleneck (VNB) in data-intensive applications.... » read more

Hardware-Assisted Malware Analysis
By Technical Paper Link - 25 Aug, 2023 - Comments: 0

A technical paper titled "On the Feasibility of Malware Unpacking via Hardware-assisted Loop Profiling" was published by researches at Shandong University & Hubei Normal University, Tulane University and University of Texas at Arlington.  This paper was included at the recent 32nd USENIX Security Symposium. Abstract "Hardware Performance Counters (HPCs) are built-in registers of modern... » read more

Transient Execution Attacks That Leaks Arbitrary Kernel Memory (ETH Zurich)
By Technical Paper Link - 25 Aug, 2023 - Comments: 0

A technical paper titled “Inception: Exposing New Attack Surfaces with Training in Transient Execution” was published by researchers at ETH Zurich. Abstract: "To protect against transient control-flow hijacks, software relies on a secure state of microarchitectural buffers that are involved in branching decisions. To achieve this secure state, hardware and software mitigations restrict or... » read more

Modeling and Testing Microarchitectural Leakage of CPU Exceptions (Microsoft, Vrije Universiteit Amsterdam)
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "Speculation at Fault: Modeling and Testing Microarchitectural Leakage of CPU Exceptions" was published by researchers at Microsoft and Vrije Universiteit Amsterdam. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "Microarchitectural leakage models provide effective tools to prevent vulnerabilities such as Spectre and Meltdown vi... » read more

Microarchitectural Side-Channel Attacks And Defenses on NVRAM DIMMs
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems" was published by researchers at UC San Diego, Purdue University, and UT Austin. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We study microarchitectural side-channel attacks and defenses on non-volatile RAM (NVRAM) DIMMs. In this study, we first perform r... » read more

Formal Processor Model Providing Provably Secure Speculation For The Constant-Time Policy
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A new technical paper titled "ProSpeCT: Provably Secure Speculation for the Constant-Time Policy" was published by researchers at imec-DistriNet, KU Leuven, CEA, and INRIA. This paper was included at the recent 32nd USENIX Security Symposium. Abstract: "We propose ProSpeCT, a generic formal processor model providing provably secure speculation for the constant-time policy. For constant-tim... » read more

Remote Direct Memory Introspection (Rice, Duke, MIT)
By Technical Paper Link - 22 Aug, 2023 - Comments: 0

A technical paper titled "Remote Direct Memory Introspection" was published by researchers at Rice University, Duke University, and MIT. This paper won a distinguished paper award at the recent 32nd USENIX Security Symposium. Abstract: "Hypervisors have played a critical role in cloud security, but they introduce a large trusted computing base (TCB) and incur a heavy performance tax. As of... » read more

EDA Tool To Detect SW-HW Vulnerabilities Ensuring Data Confidentiality In A RISC-V Architecture
By Technical Paper Link - 18 Aug, 2023 - Comments: 0

A technical paper titled “SoftFlow: Automated HW-SW Confidentiality Verification for Embedded Processors” was published by researchers at RWTH Aachen University, Robert Bosch, and Newcastle University. Abstract: "Despite its ever-increasing impact, security is not considered as a design objective in commercial electronic design automation (EDA) tools. This results in vulnerabilities being... » read more

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