category: Architectures

category: IoT, Security & Automotive

Fault Awareness And Reliability Improvements In a Fault-Tolerant RISC-V SoC (HARV-SoC)
By Technical Paper Link - 24 Jun, 2023 - Comments: 0

A technical paper titled “Enhancing Fault Awareness and Reliability of a Fault-Tolerant RISC-V System-on-Chip” was published by researchers at University of Montpellier and University of Vale do Itajaí. Abstract: "Recent research has shown interest in adopting the RISC-V processors for high-reliability electronics, such as aerospace applications. The openness of this architecture enables... » read more

An Energy Efficient, Linux-Capable RISC-V Host Platform Designed For The Seamless Plug-In And Control Of Domain-Specific Accelerators
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In” was published by researchers at ETH Zurich and University of Bologna. Abstract: "Power and cost constraints in the internet-of-things (IoT) extreme-edge and TinyML domains, coupled with increasing performance requirements, motivate a trend toward heterogeneous arc... » read more

Tools for Co-Designing HPC Systems Using RISC-V As A Demonstrator
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Software Development Vehicles to enable extended and early co-design: a RISC-V and HPC case of study” was published by researchers at Barcelona Supercomputing Center and FORTH. Abstract: "Prototyping HPC systems with low-to-mid technology readiness level (TRL) systems is critical for providing feedback to hardware designers, the system software team (e.g., co... » read more

Uncovering The Size, Structure, And Operation Of DRAM Subarrays And Showing Experimental Results Supporting The Cause Of Rowhammer
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “X-ray: Discovering DRAM Internal Structure and Error Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for accurate information about the internal structure and characteristics of dynamic random-access memory (DRAM) has been on the rise. Recen... » read more

End-To-End System Architecture For Quantum RAM (Yale, AWS, Caltech)
By Technical Paper Link - 14 Jun, 2023 - Comments: 0

A technical paper titled “Systems Architecture for Quantum Random Access Memory” was published by researchers at Yale University, AWS Center for Quantum Computing, and California Institute of Technology. Abstract: "Operating on the principles of quantum mechanics, quantum algorithms hold the promise for solving problems that are beyond the reach of the best-available classical algorithms.... » read more

Advantages, Disadvantages, And Use Cases Of FPGAs
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “Data Processing with FPGAs on Modern Architectures” was published by researchers at ETH Zürich. Abstract: "Trends in hardware, the prevalence of the cloud, and the rise of highly demanding applications have ushered an era of specialization that is quickly changing the way data is processed at scale. These changes are likely to continue and accelerate in the next... » read more

3DICs: Legalizer Techniques For Better Routing Quality, Fewer DRVs, And Reduced Total Slack With Negligible Runtime Impact
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “On Legalization of Die Bonding Bumps and Pads for 3D ICs” was published by researchers at the Georgia Institute of Technology, NVIDIA Corporation, and the University of Bremen. Abstract "State-of-the-art 3D IC Place-and-Route flows were designed with older technology nodes and aggressive bonding pitch assumptions. As a result, these flows fail to honor the widt... » read more

A PIM Architecture That Supports Floating Point-Precision Computations Within The Memory Chip
By Technical Paper Link - 07 Jun, 2023 - Comments: 0

A technical paper titled “FlutPIM: A Look-up Table-based Processing in Memory Architecture with Floating-point Computation Support for Deep Learning Applications” was published by researchers at Rochester Institute of Technology and George Mason University. Abstract: "Processing-in-Memory (PIM) has shown great potential for a wide range of data-driven applications, especially Deep Learnin... » read more

Framework To Compile Quantum Programs Onto Chiplets (UCSB, Cisco)
By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "Compilation for Quantum Computing on Chiplets" was published by researchers at UC Santa Barbara and Cisco Quantum Lab. Abstract: "Chiplet architecture is an emerging architecture for quantum computing that could significantly increase qubit resources with its great scalability and modularity. However, as the computing scale increases, communication between qubits w... » read more

Hardware Security: Eliminating/Reducing A Blind Spot of Side Channels (CISPA Helmholtz Center for Information Security)
By Technical Paper Link - 03 Jun, 2023 - Comments: 0

A technical paper titled "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channels" was published by researchers at CISPA Helmholtz Center for Information Security. Abstract: "In the last years, there has been a rapid increase in microarchitectural attacks, exploiting side effects of various parts of the CPU. Most of them have in common that they rely ... » read more

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