category: Architectures

category: IoT, Security & Automotive

Inter-Chiplet Interconnect Topologies On Organic And Glass Substrates
By Technical Paper Link - 29 Apr, 2025 - Comments: 0

A new technical paper titled "FoldedHexaTorus: An Inter-Chiplet Interconnect Topology for Chiplet-based Systems using Organic and Glass Substrates" was published by researchers at ETH Zurich. Abstract "Chiplet-based systems are rapidly gaining traction in the market. Two packaging options for such systems are the established organic substrates and the emerging glass substrates. These substr... » read more

Challenges of Chiplet Placement And Routing Optimization (KAIST)
By Technical Paper Link - 23 Apr, 2025 - Comments: 0

A new technical paper titled "Advanced Chiplet Placement and Routing Optimization considering Signal Integrity" was published by researchers at KAIST. Abstract: "This article addresses the critical challenges of chiplet placement and routing optimization in the era of advanced packaging and heterogeneous integration. We present a novel approach that formulates the problem as a signal integr... » read more

Single Transistor Memory Cell C2RAM Based On FDSOI For Quantum And Neuromorphic
By Technical Paper Link - 15 Apr, 2025 - Comments: 0

A new technical paper titled "An Energy Efficient Memory Cell for Quantum and Neuromorphic Computing at Low Temperatures" was published by researchers at Forschungszentrum Jülich, RWTH Aachen University and SOITEC. Abstract: "Efficient computing in cryogenic environments, including classical von Neumann, quantum, and neuromorphic systems, is poised to transform big data processing. The que... » read more

ReRAM-Based, In-Memory Implementation Of Stochastic Computing
By Technical Paper Link - 14 Apr, 2025 - Comments: 0

A new technical paper titled "All-in-Memory Stochastic Computing using ReRAM" was published by researchers at TU Dresden, Center for Scalable Data Analytics and Artificial Intelligence (ScaDS.AI), Case Western Reserve University, University of Louisiana at Lafayette and Barkhausen Institut. Abstract "As the demand for efficient, low-power computing in embedded and edge devices grows, tradit... » read more

Cache Coherence In Network On Chip Design (NTU)
By Technical Paper Link - 08 Apr, 2025 - Comments: 0

A new technical paper titled "Learning Cache Coherence Traffic for NoC Routing Design" was published by researchers at Nanyang Technological University. "In this work, we propose a cache coherence-aware routing approach with integrated topology selection, guided by our Cache Coherence Traffic Analyzer (CCTA). Our method achieves up to 10.52% lower packet latency, 55.51% faster execution time... » read more

Side-by-Side Benchmark of NPU Platforms (Imperial College London, Cambridge)
By Technical Paper Link - 05 Apr, 2025 - Comments: 0

A new technical paper titled "Benchmarking Ultra-Low-Power μNPUs" was published by researchers at Imperial College London and University of Cambridge. Abstract "Efficient on-device neural network (NN) inference has various advantages over cloud-based processing, including predictable latency, enhanced privacy, greater reliability, and reduced operating costs for vendors. This has sparked t... » read more

Emerging Cybersecurity Risks in Connected Vehicles, With Focus On In-Vehicle and Vehicle-Edge Platforms
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "Security Risks and Designs in the Connected Vehicle Ecosystem: In-Vehicle and Edge Platforms" was published by researchers at Università di Pisa, Ford Motor Company, MIT, and the Institute of Informatics and Telematics (Pisa). Abstract "The evolution of Connected Vehicles (CVs) has introduced significant advancements in both in-vehicle and vehicle-edge platfor... » read more

Adaptive RISC-V Cache Architecture for Near-Memory Extensions (Politecnico di Torino, EPFL)
By Technical Paper Link - 04 Apr, 2025 - Comments: 0

A new technical paper titled "ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions" was published by researchers at Politecnico di Torino and EPFL. Abstract "Modern data-driven applications expose limitations of von Neumann architectures - extensive data movement, low throughput, and poor energy efficiency. Accelerators improve performance but lack flexibility and require... » read more

Reverse Engineering NVIDIA GPU Cores (Universitat Politècnica de Catalunya)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Analyzing Modern NVIDIA GPU cores" was published by Universitat Politècnica de Catalunya. Abstract "GPUs are the most popular platform for accelerating HPC workloads, such as artificial intelligence and science simulations. However, most microarchitectural research in academia relies on GPU core pipeline designs based on architectures that are more than 15 yea... » read more

Scalable And Energy Efficient Solution for Hardware-Based ANNs (KAUST, NUS)
By Technical Paper Link - 30 Mar, 2025 - Comments: 0

A new technical paper titled "Synaptic and neural behaviours in a standard silicon transistor" was published by researchers at KAUST and National University of Singapore. Abstract "Hardware implementations of artificial neural networks (ANNs)—the most advanced of which are made of millions of electronic neurons interconnected by hundreds of millions of electronic synapses—have achieved ... » read more

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