category: Architectures

category: IoT, Security & Automotive

CAM-Based CMOS Implementation Of Reference Frames For Neuromorphic Processors (Carnegie Mellon U.)
By Technical Paper Link - 31 May, 2024 - Comments: 0

A technical paper titled “NeRTCAM: CAM-Based CMOS Implementation of Reference Frames for Neuromorphic Processors” was published by researchers at Carnegie Mellon University. Abstract: "Neuromorphic architectures mimicking biological neural networks have been proposed as a much more efficient alternative to conventional von Neumann architectures for the exploding compute demands of AI work... » read more

A HW-Aware Scalable Exact-Attention Execution Mechanism For GPUs (Microsoft)
By Technical Paper Link - 21 May, 2024 - Comments: 0

A technical paper titled “Lean Attention: Hardware-Aware Scalable Attention Mechanism for the Decode-Phase of Transformers” was published by researchers at Microsoft. Abstract: "Transformer-based models have emerged as one of the most widely used architectures for natural language processing, natural language generation, and image generation. The size of the state-of-the-art models has in... » read more

Ferroelectric Memory-Based IMC for ML Workloads
By Technical Paper Link - 21 May, 2024 - Comments: 0

A new technical paper titled "Ferroelectric capacitors and field-effect transistors as in-memory computing elements for machine learning workloads" was published by researchers at Purdue University. Abstract "This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate mach... » read more

DRAM Microarchitectures And Their Impacts On Activate-Induced Bitflips Such As RowHammer 
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “DRAMScope: Uncovering DRAM Microarchitecture and Characteristics by Issuing Memory Commands” was published by researchers at Seoul National University and University of Illinois at Urbana-Champaign. Abstract: "The demand for precise information on DRAM microarchitectures and error characteristics has surged, driven by the need to explore processing in memory, enh... » read more

Competitive Open-Source EDA Tools
By Technical Paper Link - 19 May, 2024 - Comments: 0

A technical paper titled “Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC” was published by researchers at ETH Zurich and University of Bologna. Abstract: "We introduce Basilisk, an optimized application-specific integrated circuit (ASIC) implementation and design flow building on the end-to-end open-source Iguana system-on-chip (... » read more

Ultra Energy-Efficient HW Platform For Neuromorphic Computing Enabled By 2D-TMD Tunnel-FETs (UC Santa Barbara)
By Technical Paper Link - 07 May, 2024 - Comments: 0

A technical paper titled “An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs” was published by researchers at the University of California Santa Barbara. Abstract: "Brain-like energy-efficient computing has remained elusive for neuromorphic (NM) circuits and hardware platform implementations despite decades of research. In this work we rev... » read more

New Ways To Optimize GEMM-Based Applications Targeting Two Leading AI-Optimized FPGA Architectures
By Technical Paper Link - 07 May, 2024 - Comments: 0

A technical paper titled “Efficient Approaches for GEMM Acceleration on Leading AI-Optimized FPGAs” was published by researchers at The University of Texas at Austin and Arizona State University. Abstract: "FPGAs are a promising platform for accelerating Deep Learning (DL) applications, due to their high performance, low power consumption, and reconfigurability. Recently, the leading FPGA... » read more

Optimizing Offload Performance In Heterogeneous Multi-Processor SoCs (ETH Zurich)
By Technical Paper Link - 03 May, 2024 - Comments: 0

A technical paper titled “Optimizing Offload Performance in Heterogeneous MPSoCs” was published by researchers at ETH Zurich. Abstract: "Heterogeneous multi-core architectures combine a few "host" cores, optimized for single-thread performance, with many small energy-efficient "accelerator" cores for data-parallel processing, on a single chip. Offloading a computation to the many-core acc... » read more

Merging Power and Arithmetic Optimization Via Datapath Rewriting (Intel, Imperial College London)
By Technical Paper Link - 19 Apr, 2024 - Comments: 0

A new technical paper titled "Combining Power and Arithmetic Optimization via Datapath Rewriting" was published by researchers at Intel Corporation and Imperial College London. Abstract: "Industrial datapath designers consider dynamic power consumption to be a key metric. Arithmetic circuits contribute a major component of total chip power consumption and are therefore a common target for p... » read more

In-Memory Computing: Techniques for Error Detection and Correction
By Technical Paper Link - 16 Apr, 2024 - Comments: 0

A new technical paper titled "Error Detection and Correction Codes for Safe In-Memory Computations" was published by researchers at Robert Bosch, Forschungszentrum Julich, and Newcastle University. Abstract "In-Memory Computing (IMC) introduces a new paradigm of computation that offers high efficiency in terms of latency and power consumption for AI accelerators. However, the non-idealities... » read more

← Older posts Newer posts →

  • Sponsors

About

Navigation

Connect With Us

Copyright ©2013-2025 SMG   |  Terms of Service  |  Privacy Policy