category: Design & Verification

category: IoT, Security & Automotive

Pooling CPU Memory for LLM Inference With Lower Latency and Higher Throughput (UC Berkeley)
By Technical Paper Link - 26 Nov, 2024 - Comments: 0

A new technical paper titled "Pie: Pooling CPU Memory for LLM Inference" was published by researchers at UC Berkeley. Abstract "The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping ofte... » read more

Sustainable Hardware Specialization Through Reconfigurable Logic (NUS, Ghent Univ.)
By Technical Paper Link - 15 Nov, 2024 - Comments: 0

A  new technical paper titled "Sustainable Hardware Specialization" was published by researchers at National University of Singapore and Ghent University. "We explore sustainable hardware specialization through reconfigurable logic that has the potential to drastically reduce the environmental footprint compared to a sea of accelerators by amortizing its embodied footprint across multiple a... » read more

Dedicated 3D Accelerator Specifically Designed For Emerging Spiking Transformers
By Technical Paper Link - 13 Nov, 2024 - Comments: 0

A new technical paper titled "Spiking Transformer Hardware Accelerators in 3D Integration" was published by researchers at UC Santa Barbara, Georgia Tech and Burapha University. "Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architect... » read more

Improving Power and Speed in GAA-NS FETs
By Technical Paper Link - 11 Nov, 2024 - Comments: 0

A new technical paper titled "Design Decoupling of Inner-and Outer-Gate Lengths in Nanosheet FETs for Ultimate Scaling" was published by researchers at Belgium Research Center, Huawei Technologies and Global TCAD Solutions. Abstract: "Using a full design-technology-co-optimization (DTCO) methodology, we show the advantages of design decoupling of inner -and outer-gates in gate-all-around ... » read more

Benchmark and Evaluation Framework For Characterizing LLM Performance In Formal Verification (UC Berkeley, Nvidia)
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "FVEval: Understanding Language Model Capabilities in Formal Verification of Digital Hardware" was published by researchers at UC Berkeley and NVIDIA. Abstract "The remarkable reasoning and code generation capabilities of large language models (LLMs) have spurred significant interest in applying LLMs to enable task automation in digital chip design. In particula... » read more

Pre-Silicon Verification Method Addressing Critical Aspects of Speculative Execution Vulnerability Detection
By Technical Paper Link - 04 Nov, 2024 - Comments: 0

A new technical paper titled "Lost and Found in Speculation: Hybrid Speculative Vulnerability Detection" was published by researchers at Technical University of Darmstadt and Texas A&M University. "We introduce Specure, a novel pre-silicon verification method composing hardware fuzzing with Information Flow Tracking (IFT) to address speculative execution leakages. Integrating IFT enables two... » read more

Metamodeling Techniques for Formal Verification
By Technical Paper Link - 29 Oct, 2024 - Comments: 0

A new technical paper titled "Verifying Non-friendly Formal Verification Designs: Can We Start Earlier?" was published by researchers at Universität Kaiserslautern-Landau and Infineon Technologies. Published in DVCon Europe 2024. Abstract "The design of Systems on Chips (SoCs) is becoming more and more complex due to technological advancements. Missed bugs can cause drastic failures in saf... » read more

Overview Of Security Verification Methodologies for SoC Designs Pre-Silicon (U. of Florida)
By Technical Paper Link - 23 Oct, 2024 - Comments: 0

A technical paper titled "A Survey on SoC Security Verification Methods at the Pre-silicon Stage" was recently published by researchers at University of Florida. Abstract "This paper presents a survey of the state-of-the-art pre-silicon security verification techniques for System-on-Chip (SoC) designs, focusing on ensuring that designs, implemented in hardware description languages (HDLs) a... » read more

Formally Modeling and Verifying CXL Cache Coherence (Imperial College London)
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "Formalising CXL Cache Coherence" was published by researchers at Imperial College London. Abstract "We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English spec... » read more

Open-Source, Chiplet-Compatible RISC-V Controller
By Technical Paper Link - 22 Oct, 2024 - Comments: 0

A new technical paper titled "ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package" was published by researchers at ETH Zurich and University of Bologna. Abstract "The increasing complexity of real-time control algorithms and the trend toward 2.5D technology necessitate the development of scalable controllers for managing the complex, integrated oper... » read more

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