category: Design & Verification

category: IoT, Security & Automotive

Processing-Using-DRAM: Attaining High-Performance Via Dynamic Precision Bit-Serial Arithmetic (ETH Zurich, et al.)
By Technical Paper Link - 01 Feb, 2025 - Comments: 0

A new technical paper titled "Proteus: Achieving High-Performance Processing-Using-DRAM via Dynamic Precision Bit-Serial Arithmetic" was published by researchers at ETH Zurich, Cambridge University, Universidad de Córdoba, Univ. of Illinois Urbana-Champaign and NVIDIA Research. Abstract "Processing-using-DRAM (PUD) is a paradigm where the analog operational properties of DRAM structures ... » read more

Topology And Connection Architecture Of CXL Pooling Systems (Microsoft, Columbia)
By Technical Paper Link - 29 Jan, 2025 - Comments: 0

A new technical paper titled "Octopus: Scalable Low-Cost CXL Memory Pooling" was published by researchers at University of Washington, Microsoft Azure and Columbia University. Abstract "Compute Express Link (CXL) is widely-supported interconnect standard that promises to enable memory disaggregation in data centers. CXL allows for memory pooling, which can be used to create a shared memory ... » read more

DeepSeek: Improving Language Model Reasoning Capabilities Using Pure Reinforcement Learning
By Technical Paper Link - 27 Jan, 2025 - Comments: 0

A new technical paper titled "DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning" was published by DeepSeek. Abstract: "We introduce our first-generation reasoning models, DeepSeek-R1-Zero and DeepSeek-R1. DeepSeek-R1-Zero, a model trained via large-scale reinforcement learning (RL) without supervised fine-tuning (SFT) as a preliminary step, demonstrates rema... » read more

Reverse Engineering Approach for Evaluating HW IP Protection ( U. of Florida, Indiana U.)
By Technical Paper Link - 23 Jan, 2025 - Comments: 0

A technical paper titled "Library-Attack: Reverse Engineering Approach for Evaluating Hardware IP Protection" was published by researchers at University of Florida and Indiana University. Abstract "Existing countermeasures for hardware IP protection, such as obfuscation, camouflaging, and redaction, aim to defend against confidentiality and integrity attacks. However, within the current thr... » read more

Parallelized Compilation Pipeline Optimized for Chiplet-Based Quantum Computers
By Technical Paper Link - 21 Jan, 2025 - Comments: 0

A new technical paper titled "Modular Compilation for Quantum Chiplet Architectures" was published by researchers at Northwestern University. Abstract "As quantum computing technology continues to mature, industry is adopting modular quantum architectures to keep quantum scaling on the projected path and meet performance targets. However, the complexity of chiplet-based quantum devices, cou... » read more

Design-Space Analysis of M3D FPGA With BEOL Configuration Memories (Georgia Tech, UCLA)
By Technical Paper Link - 17 Jan, 2025 - Comments: 0

A new technical paper titled "Monolithic 3D FPGAs Utilizing Back-End-of-Line Configuration Memories" was published by researchers at Georgia Tech and UCLA. Abstract "This work presents a novel monolithic 3D (M3D) FPGA architecture that leverages stackable back-end-of-line (BEOL) transistors to implement configuration memory and pass gates, significantly improving area, latency, and power ef... » read more

Design Space for the Device-Circuit Codesign of NVM-Based CIM Accelerators (TSMC)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper/mini-review titled "Assessing Design Space for the Device-Circuit Codesign of Nonvolatile Memory-Based Compute-in-Memory Accelerators" was published by researchers at TSMC and National Tsing Hua University. Abstract "Unprecedented penetration of artificial intelligence (AI) algorithms has brought about rapid innovations in electronic hardware, including new memory devi... » read more

Geometric-Aware Model Merging Approach To Enhance Instruction Alignment in Chip LLMs (Nvidia)
By Technical Paper Link - 15 Jan, 2025 - Comments: 0

A new technical paper titled "ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic Interpolation" was published by researchers at NVIDIA Research. Abstract: "Recent advancements in large language models (LLMs) have expanded their application across various domains, including chip design, where domain-adapted chip models like ChipNeMo have emerged. However, ... » read more

Schottky Barrier Transistors: Status, Challenges and Modeling Tools
By Technical Paper Link - 08 Jan, 2025 - Comments: 0

A technical paper titled "Roadmap for Schottky barrier transistors" was published by researchers at University of Surrey, Namlab gGmbH, Forschungszentrum Jülich (FZJ), et al. Abstract "In this roadmap we consider the status and challenges of technologies that use the properties of a rectifying metal-semiconductor interface, known as a Schottky barrier (SB), as an asset for device functio... » read more

Designing Heterogeneous AI Acceleration SoCs
By Technical Paper Link - 06 Jan, 2025 - Comments: 0

A new technical paper titled "Open-Source Heterogeneous SoCs for AI: The PULP Platform Experience" was published by researchers at University of Bologna. Abstract "Since 2013, the PULP (Parallel Ultra-Low Power) Platform project has been one of the most active and successful initiatives in designing research IPs and releasing them as open-source. Its portfolio now ranges from processor co... » read more

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